fix syntax error and some wrong variables sizes

hdl/rtl/EF_UART.v

@@ -266,7 +266,7 @@ module UART_RX #(parameter NUM_SAMPLES = 16, MDW = 8)(
     reg [3:0]   b_reg;            //baud-rate/over sampling counter
     reg [3:0]   b_next;
     reg [3:0]   count_reg;        //data-bit counter
-    reg [2:0]   count_next;
+    reg [3:0]   count_next;
     reg [8:0]   data_reg;         //data register
     reg [8:0]   data_next;
     reg         p_error_reg;
@@ -308,6 +308,7 @@ module UART_RX #(parameter NUM_SAMPLES = 16, MDW = 8)(
         data_next = data_reg;
         rx_done = 1'b0;
         p_error_next = 1'b0;
+        f_error_next = 1'b0;
 
         case(current_state)
             idle_st:
@@ -441,16 +442,16 @@ module UART_TX #(parameter NUM_SAMPLES = 16, MDW = 8)(
     reg [2:0]   next_state;
     reg [3:0]   b_reg;          // baud tick counter
     reg [3:0]   b_next;
-    reg [2:0]   count_reg;      // data bit counter
-    reg [2:0]   count_next;
+    reg [3:0]   count_reg;      // data bit counter
+    reg [3:0]   count_next;
     reg [8:0]   data_reg;       // data register
     reg [8:0]   data_next;
     reg         tx_reg;         // output data reg
     reg         tx_next;
 
     	// prepare the data to claculate the parity by removing any extra bits entered
 	// by the user by error
-    	wire [MDW-1] pdata = (d_in) & ~(MDW'hFF << data_size);
+    	wire [MDW-1] pdata = (d_in) & ~({MDW{1'b1}} << data_size);
 
     //State Machine  
     always @(posedge clk, negedge resetn) begin

hdl/rtl/bus_wrappers/EF_UART_APB.v

@@ -243,7 +243,7 @@ module EF_UART_APB #(
 	assign PREADY = 1'b1;
 
 	assign	RXDATA_WIRE = rdata;
-	assign	rd = (apb_re & (PADDR[`APB_AW-1:0] == RXDATA_REG_OFFSET) & PENABLE);
+	assign	rd = (apb_re & (PADDR[`APB_AW-1:0] == RXDATA_REG_OFFSET));
 	assign	wdata = PWDATA;
 	assign	wr = (apb_we & (PADDR[`APB_AW-1:0] == TXDATA_REG_OFFSET));
 endmodule