Skip to content

Issues: efabless/EF_UART

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

9 Open 8 Closed
9 Open 8 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

Fifo reading might stuck depending on AHB bug Something isn't working
#27 opened Oct 9, 2024 by M0stafaRady
@shalan
Documentation incomplete
#25 opened Aug 20, 2024 by marwaneltoukhy
WB wrapper synthesis issue
#24 opened Aug 20, 2024 by marwaneltoukhy
unit tests fail
#23 opened Aug 20, 2024 by marwaneltoukhy
there are 2 files for each bus wrapper
#22 opened Aug 20, 2024 by marwaneltoukhy
Missing modules that start with aucohl
#21 opened Aug 20, 2024 by marwaneltoukhy
Ensure consistency of IP Utilities modules and macros usage in all IPs
#20 opened Jun 15, 2024 by NouranAbdelaziz
unmapped cells in synthesis
#19 opened May 2, 2024 by M0stafaRady
@shalan
1
Enhancing UART Transmission Integrity: Suggestions for Mid-Transmission Disruptions enhancement New feature or request
#6 opened Jan 16, 2024 by M0stafaRady
ProTip! Type g p on any issue or pull request to go back to the pull request listing page.