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update make file with ip_utilities for uvm verification
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M0stafaRady committed Feb 25, 2024
1 parent eb85d17 commit b7a72fc
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Showing 4 changed files with 10 additions and 319 deletions.
3 changes: 2 additions & 1 deletion verify/uvm-python/.gitignore
Original file line number Diff line number Diff line change
Expand Up @@ -9,4 +9,5 @@
/coverageReports/
*.xml
*.gtkw
/EF_UVM/
/EF_UVM/
IP_Utilities/
12 changes: 8 additions & 4 deletions verify/uvm-python/Makefile
Original file line number Diff line number Diff line change
@@ -1,15 +1,15 @@
PLUSARGS += "+UVM_VERBOSITY=UVM_HIGH"
TOPLEVEL := top
MODULE ?= top_module
VERILOG_SOURCES ?= $(PWD)/top.v $(PWD)/../../hdl/rtl/bus_wrappers/EF_UART_APB.v $(PWD)/../../hdl/rtl/EF_UART.v
VERILOG_SOURCES ?= $(PWD)/top.v $(PWD)/IP_Utilities/rtl/aucohl_lib.v $(PWD)/IP_Utilities/rtl/aucohl_rtl.vh $(PWD)/../../hdl/rtl/bus_wrappers/EF_UART_APB.pp.v $(PWD)/../../hdl/rtl/EF_UART.v
RTL_MACROS ?= ""
# RTL_MACROS ?= "-DSKIP_WAVE_DUMP"
YAML_FILE = $(PWD)/../../EF_UART.yaml
MAKEFLAGS += --no-print-directory

# List of tests
TESTS := TX_StressTest RX_StressTest LoopbackTest PrescalarStressTest LengthParityTXStressTest LengthParityRXStressTest WriteReadRegsTest
# TESTS := WriteReadRegsTest
TESTS := WriteReadRegsTest

# Variable for tag - set this as required
SIM_TAG ?= default_tag
Expand All @@ -18,9 +18,13 @@ SIM_TAG ?= default_tag
SIM_PATH := $(PWD)/sim/$(SIM_TAG)

# Check and clone EF_UVM repository at the beginning of the Makefile execution
REPO_DIR := EF_UVM

clone_ef_uvm := $(shell if [ ! -d "$(REPO_DIR)" ]; then \
clone_ip_util := $(shell if [ ! -d "IP_Utilities" ]; then \
echo "Cloning the IP_Utilities repository..."; \
git clone https://github.com/shalan/IP_Utilities.git; \
fi;)

clone_ef_uvm := $(shell if [ ! -d "EF_UVM" ]; then \
echo "Cloning the EF_UVM repository..."; \
git clone https://github.com/M0stafaRady/EF_UVM.git; \
fi;)
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46 changes: 0 additions & 46 deletions verify/uvm-python/apb_wrapper.vh

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268 changes: 0 additions & 268 deletions verify/uvm-python/aucohl_lib.v

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