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[GSOC] integrated support for Zvbc #42

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SyedHassanUlHaq
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SyedHassanUlHaq and others added 2 commits August 8, 2024 13:46
refactored generator for sew64Only insn

Co-authored-by: Yang Liu <[email protected]>
@ksco
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ksco commented Aug 16, 2024

Sorry, why this is closed?

@SyedHassanUlHaq
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Sorry, why this is closed?

My GSOC mentor Zewen told me that we are not going to support some instructions with SEW=64.
So we can skip these SEW=64 instructions and I can close the PR

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ksco commented Aug 17, 2024

Okay, but the PR is good, so why not merge it? I just need an explanation about valid SEW values.

@SyedHassanUlHaq
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image

here it states that LMUL >= SEWmin/ELEN. So for a instruction that only supports SEW=64, SEWmin=64 and ELEN=64
Hence LMUL >= 1

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ksco commented Aug 17, 2024

I see, can you make another PR so we can merge this in?

@SyedHassanUlHaq
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sure

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2 participants