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chipsalliance / riscv-vector-tests Public

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[GSOC] integrated support for Zvbc#42

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SyedHassanUlHaq wants to merge 4 commits intochipsalliance:mainchipsalliance/riscv-vector-tests:mainfrom SyedHassanUlHaq:mainSyedHassanUlHaq/riscv-vector-tests:mainCopy head branch name to clipboard

+100-3

Conversation Commits4 (4)Checks Files changed

Commits

Commits on Aug 7, 2024

[GSOC] added configs for Zvbc insn
SyedHassanUlHaq
committed
[GSOC] modified vdvs2rs1vm generator for sew64 reserved insn
SyedHassanUlHaq
committed

Commits on Aug 8, 2024

[GSOC] modified vdvs2vs1vm generator for sew64 reserved insn

SyedHassanUlHaq
and
ksco
committed
fixed
SyedHassanUlHaq
committed

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