fixed

chipsalliance · Aug 8, 2024 · cda6fab · cda6fab
1 parent 9b115bb
commit cda6fab
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Showing 2 changed files with 6 additions and 6 deletions.
diff --git a/generator/insn_vdvs2rs1vm.go b/generator/insn_vdvs2rs1vm.go
@@ -9,15 +9,15 @@ import (
 func (i *Insn) genCodeVdVs2Rs1Vm(pos int) []string {
 	vdWidening := strings.HasPrefix(i.Name, "vw")
 	vs2Widening := strings.HasSuffix(i.Name, ".wx")
-	sew64Only := strings.HasSuffix(i.Name, "vclmul")
+	sew64Only := strings.HasPrefix(i.Name, "vclmul")
 	vdSize := iff(vdWidening, 2, 1)
 	vs2Size := iff(vs2Widening, 2, 1)
 
 	sews := iff(vdWidening || vs2Widening, allSEWs[:len(allSEWs)-1], allSEWs)
-	sews = iff(sew64_insn, []SEW{64}, sews)
+	sews = iff(sew64Only, []SEW{64}, sews)
 
 	combinations := i.combinations(
-		iff(vdWidening || vs2Widening, wideningMULs, iff(sew64_insn, []LMUL{1, 2, 4, 8}, allLMULs)),
+		iff(vdWidening || vs2Widening, wideningMULs, iff(sew64Only, []LMUL{1, 2, 4, 8}, allLMULs)),
 		sews,
 		[]bool{false, true},
 		i.vxrms(),

diff --git a/generator/insn_vdvs2vs1vm.go b/generator/insn_vdvs2vs1vm.go
@@ -8,17 +8,17 @@ import (
 
 func (i *Insn) genCodeVdVs2Vs1Vm(pos int) []string {
 	float := strings.HasPrefix(i.Name, "vf") || strings.HasPrefix(i.Name, "vmf")
-	sew64_insn := i.Name == "vclmul.vv" || i.Name == "vclmulh.vv"
+	sew64Only := strings.HasPrefix(i.Name, "vclmul")	
 	vdWidening := strings.HasPrefix(i.Name, "vw") || strings.HasPrefix(i.Name, "vfw")
 	vs2Widening := strings.HasSuffix(i.Name, ".wv")
 	vdSize := iff(vdWidening, 2, 1)
 	vs2Size := iff(vs2Widening, 2, 1)
 
 	sews := iff(float, floatSEWs, allSEWs)
 	sews = iff(vdWidening || vs2Widening, sews[:len(sews)-1], sews)
-    sews = iff(sew64_insn, []SEW{64}, sews)
+    sews = iff(sew64Only, []SEW{64}, sews)
 	combinations := i.combinations(
-		iff(vdWidening || vs2Widening, wideningMULs, iff(sew64_insn, []LMUL{1, 2, 4, 8}, allLMULs)),
+		iff(vdWidening || vs2Widening, wideningMULs, iff(sew64Only, []LMUL{1, 2, 4, 8}, allLMULs)),
 		sews,
 		[]bool{false, true},
 		i.vxrms(),