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Litex soc now use explicit async read ram blackbox Scala CI #388: Commit 43195dd pushed by Dolu1990
July 10, 2024 07:25 58m 1s main
main
July 10, 2024 07:25 58m 1s
sync SpinalHDL Scala CI #387: Commit 3dca887 pushed by Dolu1990
July 10, 2024 07:17 57m 57s main
main
July 10, 2024 07:17 57m 57s
Fix the check of the register Rd is not equal to zero for c.lwsp instruction and Update IO rang addresses Scala CI #386: Pull request #115 synchronize by Bill94l
July 8, 2024 12:50 57m 18s Bill94l:main
Bill94l:main
July 8, 2024 12:50 57m 18s
Fix the check of the register Rd is not equal to zero for c.lwsp instruction and Update IO rang addresses Scala CI #385: Pull request #115 opened by Bill94l
July 4, 2024 08:56 58m 59s Bill94l:main
Bill94l:main
July 4, 2024 08:56 58m 59s
relative spinal Scala CI #384: Commit 1cc2b23 pushed by Dolu1990
July 4, 2024 07:30 1h 2m 9s relative_sbt
relative_sbt
July 4, 2024 07:30 1h 2m 9s
Fix #112 mstatus.tw Scala CI #383: Commit bc18f66 pushed by Dolu1990
July 4, 2024 07:29 57m 49s relative_sbt
relative_sbt
July 4, 2024 07:29 57m 49s
Fix #112 mstatus.tw Scala CI #382: Commit bc18f66 pushed by Dolu1990
July 3, 2024 07:31 1h 5m 48s main
main
July 3, 2024 07:31 1h 5m 48s
Fix #112 mstatus.tw Scala CI #381: Commit 6f73692 pushed by Dolu1990
July 3, 2024 07:05 1h 5m 44s main
main
July 3, 2024 07:05 1h 5m 44s
Fix #112 mstatus.tw Scala CI #380: Commit 31e9db6 pushed by Dolu1990
July 3, 2024 07:00 1h 6m 3s main
main
July 3, 2024 07:00 1h 6m 3s
git action cache fix? Scala CI #379: Commit 298e5ea pushed by Dolu1990
May 31, 2024 14:10 1h 7m 18s main
main
May 31, 2024 14:10 1h 7m 18s
Fix #101 Scala CI #378: Commit 3008ac6 pushed by Dolu1990
May 31, 2024 08:23 9m 19s main
main
May 31, 2024 08:23 9m 19s
Fix #104 Scala CI #377: Commit c5e4d74 pushed by Dolu1990
May 30, 2024 17:03 9m 7s main
main
May 30, 2024 17:03 9m 7s
Fix #105 Scala CI #376: Commit 9115f12 pushed by Dolu1990
May 30, 2024 16:28 1h 5m 58s main
main
May 30, 2024 16:28 1h 5m 58s
Fix #106 #103 Scala CI #375: Commit ed2df82 pushed by Dolu1990
May 30, 2024 14:58 1h 7m 5s main
main
May 30, 2024 14:58 1h 7m 5s
Fix https://github.com/SpinalHDL/NaxRiscv/issues/103 Scala CI #374: Commit e5f3abb pushed by Dolu1990
May 29, 2024 14:56 1h 5m 41s main
main
May 29, 2024 14:56 1h 5m 41s
Update to Scala 2.12 and fix litex mbus offset Scala CI #373: Commit f335738 pushed by Dolu1990
April 25, 2024 14:05 11m 13s main
main
April 25, 2024 14:05 11m 13s
sync Scala CI #372: Commit ab8e27d pushed by Dolu1990
April 23, 2024 15:26 1h 8m 55s main
main
April 23, 2024 15:26 1h 8m 55s
No more self holsted action Scala CI #371: Commit 8816542 pushed by Dolu1990
March 6, 2024 10:39 1h 7m 12s main
main
March 6, 2024 10:39 1h 7m 12s
Reduce regression time Scala CI #370: Commit b0b1409 pushed by Dolu1990
March 6, 2024 10:37 1d 14h 41m 41s main
main
March 6, 2024 10:37 1d 14h 41m 41s
Merge pull request #85 from Bill94l/main Scala CI #369: Commit 646cc0f pushed by Dolu1990
March 6, 2024 10:33 1d 14h 45m 47s main
main
March 6, 2024 10:33 1d 14h 45m 47s
Merge pull request #80 from ldoolitt/main Scala CI #367: Commit 8f0bd88 pushed by Dolu1990
February 15, 2024 07:38 1d 1h 47m 10s main
main
February 15, 2024 07:38 1d 1h 47m 10s
README.md: touch-ups by a native English speaker Scala CI #366: Pull request #80 opened by ldoolitt
February 15, 2024 05:13 1d 1h 50m 48s main
main
February 15, 2024 05:13 1d 1h 50m 48s
Merge branch 'asic' Scala CI #365: Commit 75dadd3 pushed by Dolu1990
February 12, 2024 10:42 1d 14h 36m 31s main
main
February 12, 2024 10:42 1d 14h 36m 31s
Add asic option for register file blackbox Scala CI #364: Commit c750a9b pushed by Dolu1990
February 12, 2024 10:42 1d 14h 36m 55s asic
asic
February 12, 2024 10:42 1d 14h 36m 55s
cleaning Scala CI #363: Commit 0a0b2be pushed by Dolu1990
February 8, 2024 09:14 1d 0h 11m 15s asic
asic
February 8, 2024 09:14 1d 0h 11m 15s