Add asic option for register file blackbox

SpinalHDL · Feb 12, 2024 · c750a9b · c750a9b
1 parent 0a0b2be
commit c750a9b
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Showing 2 changed files with 8 additions and 4 deletions.
diff --git a/src/main/scala/naxriscv/Gen.scala b/src/main/scala/naxriscv/Gen.scala
@@ -70,6 +70,7 @@ object Config{
               withCoherency : Boolean = false,
               hartId : Int = 0,
               asic : Boolean = false,
+              withRfLatchRam : Boolean = false,
               mmuSets : Int = 32,
               regFileFakeRatio : Int = 1): ArrayBuffer[Plugin] ={
     val plugins = ArrayBuffer[Plugin]()
@@ -299,7 +300,7 @@ object Config{
       physicalDepth = 64,
       bankCount = 1,
       preferedWritePortForInit = "ALU0",
-      latchBased = asic,
+      latchBased = withRfLatchRam,
       fakeRatio = regFileFakeRatio
     )
     plugins += new CommitDebugFilterPlugin(List(4, 8, 12))
@@ -377,7 +378,7 @@ object Config{
         bankCount = 1,
         allOne = simulation,
         preferedWritePortForInit = "Fpu",
-        latchBased = asic
+        latchBased = withRfLatchRam
       )
 
       plugins += new FpuIntegerExecute("EU0")
@@ -443,8 +444,8 @@ object Config{
       case lsu: LsuPlugin =>
         lsu.addRfWriteSharing(IntRegFile, intRfWrite, withReady = false, priority = 2)
       case lsu: Lsu2Plugin =>
-        //Surprisingly doesn't make that big of a difference
-//        lsu.addRfWriteSharing(IntRegFile, intRfWrite, withReady = false, priority = 2)
+        //Surprisingly doesn't make that big of a difference on FPGA
+        if(asic) lsu.addRfWriteSharing(IntRegFile, intRfWrite, withReady = false, priority = 2)
       case eu0 : ExecutionUnitBase if eu0.euId == "EU0" =>
         eu0.addRfWriteSharing(IntRegFile, intRfWrite, withReady = true, priority = 1)
       case fpu : FpuWriteback =>

diff --git a/src/main/scala/naxriscv/platform/asic/NaxAsicGen.scala b/src/main/scala/naxriscv/platform/asic/NaxAsicGen.scala
@@ -17,6 +17,7 @@ object NaxAsicGen extends App{
   var regFileFakeRatio = 1
   var withLsu = true
   var withIoFf = false
+  var withRfLatchRam = true
   var blackBoxCombRam = false
 
   assert(new scopt.OptionParser[Unit]("NaxAsicGen") {
@@ -25,6 +26,7 @@ object NaxAsicGen extends App{
     opt[Int]("regfile-fake-ratio") action { (v, c) => regFileFakeRatio = v }
     opt[Unit]("no-lsu") action { (v, c) => withLsu = false }
     opt[Unit]("io-ff") action { (v, c) => withIoFf = true }
+    opt[Unit]("no-rf-latch-ram") action { (v, c) => withRfLatchRam = false }
     opt[Unit]("bb-comb-ram") action { (v, c) => blackBoxCombRam = true }
   }.parse(args, Unit).nonEmpty)
 
@@ -33,6 +35,7 @@ object NaxAsicGen extends App{
   def plugins = {
     val l = Config.plugins(
       asic = true,
+      withRfLatchRam = withRfLatchRam,
       withRdTime = false,
       aluCount    = 1,
       decodeCount = 1,