Merge branch 'asic'

src/main/openlane/nax/config.tcl

@@ -4,6 +4,7 @@ set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]
 set ::env(CLOCK_PORT) "clk"
 set ::env(CLOCK_PERIOD) "50.0"
 set ::env(DESIGN_IS_CORE) {1}
+set ::env(SYNTH_AUTONAME) {1}
 
 # If you use SRAM macro, uncomment this
 #set ::env(VERILOG_FILES_BLACKBOX) [glob $::env(DESIGN_DIR)/sram/*.v]

src/main/scala/naxriscv/Gen.scala

@@ -70,6 +70,8 @@ object Config{
               withCoherency : Boolean = false,
               hartId : Int = 0,
               asic : Boolean = false,
+              withRfLatchRam : Boolean = false,
+              mmuSets : Int = 32,
               regFileFakeRatio : Int = 1): ArrayBuffer[Plugin] ={
     val plugins = ArrayBuffer[Plugin]()
 
@@ -116,12 +118,12 @@ object Config{
           MmuStorageLevel(
             id    = 0,
             ways  = 4,
-            depth = 32
+            depth = mmuSets
           ),
           MmuStorageLevel(
             id    = 1,
             ways  = 2,
-            depth = 32
+            depth = mmuSets
           )
         ),
         priority = 0
@@ -196,12 +198,12 @@ object Config{
               MmuStorageLevel(
                 id = 0,
                 ways = 4,
-                depth = 32
+                depth = mmuSets
               ),
               MmuStorageLevel(
                 id = 1,
                 ways = 2,
-                depth = 32
+                depth = mmuSets
               )
             ),
             priority = 1
@@ -238,12 +240,12 @@ object Config{
               MmuStorageLevel(
                 id = 0,
                 ways = 4,
-                depth = 32
+                depth = mmuSets
               ),
               MmuStorageLevel(
                 id = 1,
                 ways = 2,
-                depth = 32
+                depth = mmuSets
               )
             ),
             priority = 1
@@ -298,7 +300,7 @@ object Config{
       physicalDepth = 64,
       bankCount = 1,
       preferedWritePortForInit = "ALU0",
-      latchBased = asic,
+      latchBased = withRfLatchRam,
       fakeRatio = regFileFakeRatio
     )
     plugins += new CommitDebugFilterPlugin(List(4, 8, 12))
@@ -333,11 +335,11 @@ object Config{
       case true => new MulPlugin(
         euId = "EU0",
         sumAt = 0,
-        sumsSpec = List((20, 2), (24, 8), (1000, 1000)),
+        sumsSpec = List((20, 4), (24, 8), (1000, 1000)),
         untilOffsetS0 = 28,
         splitWidthA = xlen,
         splitWidthB = 1,
-        useRsUnsignedPlugin = true,
+        useRsUnsignedPlugin = false,
         staticLatency = false
       )
     })
@@ -376,7 +378,7 @@ object Config{
         bankCount = 1,
         allOne = simulation,
         preferedWritePortForInit = "Fpu",
-        latchBased = asic
+        latchBased = withRfLatchRam
       )
 
       plugins += new FpuIntegerExecute("EU0")
@@ -442,8 +444,8 @@ object Config{
       case lsu: LsuPlugin =>
         lsu.addRfWriteSharing(IntRegFile, intRfWrite, withReady = false, priority = 2)
       case lsu: Lsu2Plugin =>
-        //Surprisingly doesn't make that big of a difference
-//        lsu.addRfWriteSharing(IntRegFile, intRfWrite, withReady = false, priority = 2)
+        //Surprisingly doesn't make that big of a difference on FPGA
+        if(asic) lsu.addRfWriteSharing(IntRegFile, intRfWrite, withReady = false, priority = 2)
       case eu0 : ExecutionUnitBase if eu0.euId == "EU0" =>
         eu0.addRfWriteSharing(IntRegFile, intRfWrite, withReady = true, priority = 1)
       case fpu : FpuWriteback =>

src/main/scala/naxriscv/compatibility/MultiportRam.scala

@@ -9,6 +9,8 @@ import spinal.core.internals._
 import spinal.lib._
 import spinal.lib.eda.bench.{Bench, Rtl, XilinxStdTargets}
 
+import java.io.{BufferedWriter, File, FileWriter}
+import scala.collection.mutable
 import scala.collection.mutable.ArrayBuffer
 
 case class MemWriteCmd[T <: Data](payloadType : HardType[T], depth : Int) extends Bundle{
@@ -461,4 +463,70 @@ class EnforceSyncRamPhase extends PhaseMemBlackboxing{
       typo.mem.addAttribute("ram_style", "block")
     }
   }
+}
+
+class CombRamBlackboxer(onlyTagged : Boolean = false) extends PhaseMemBlackboxing{
+  def wrapBool(that: Expression): Bool = that match {
+    case that: Bool => that
+    case that =>
+      val ret = Bool()
+      ret.assignFrom(that)
+      ret
+  }
+
+  val generatedList = mutable.LinkedHashSet[String]()
+  override def impl(pc: PhaseContext) = {
+    super.impl(pc)
+    val f = new BufferedWriter(new FileWriter(new File("comb_ram.log")))
+    for(name <- generatedList){
+      f.write(name + "\n")
+    }
+    f.close()
+  }
+
+  override def doBlackboxing(pc: PhaseContext, typo: MemTopology) : Unit = {
+    if(typo.readsSync.size == 0 && typo.readsAsync.size != 0 && typo.mem.wordCount > 8){
+      typo.writes.foreach(w => assert(w.mask == null))
+      val cd = typo.writes.head.clockDomain
+      import typo._
+
+      val ctx = List(mem.parentScope.push(), cd.push())
+
+
+      val bb = new BlackBox{
+        setDefinitionName(s"ram_${typo.readsAsync.size}ar_${typo.writes.size}w_${mem.wordCount}x${mem.width}")
+        setName(mem.getName())
+        generatedList += definitionName
+
+        val clk = in Bool()
+        mapCurrentClockDomain(clk)
+
+        val writes = Vec.fill(typo.writes.size)(new Bundle {
+          val en = in Bool()
+          val addr = in(mem.addressType)
+          val data = in(Bits(mem.width bits))
+        })
+        val reads = Vec.fill(typo.readsAsync.size)(new Bundle {
+          val addr = in(mem.addressType)
+          val data = out(Bits(mem.width bits))
+        })
+      }
+
+      for((src, dst) <- (writes, bb.writes).zipped){
+        dst.en := wrapBool(src.writeEnable) && cd.isClockEnableActive
+        dst.addr.assignFrom(src.address)
+        dst.data.assignFrom(src.data)
+      }
+
+      for ((src, dst) <- (readsAsync, bb.reads).zipped) {
+        dst.addr.assignFrom(src.address)
+        wrapConsumers(typo, src, dst.data)
+      }
+
+      mem.removeStatement()
+      mem.foreachStatements(s => s.removeStatement())
+
+      ctx.foreach(_.restore())
+    }
+  }
 }

src/main/scala/naxriscv/execute/MulPlugin.scala

@@ -149,10 +149,10 @@ class MulPlugin(val euId : String,
       // Setup the iteration variables for the next step
       sourcesSpec = addersSpec.map(_.toSource()).toList
       for ((s, m) <- (sourcesSpec, adders).zipped) sourceToSignal(s) = m
-      if(splitWidthB == 1){
-        println(addersSpec.mkString("\n"))
-        println("------------")
-      }
+//      if(splitWidthB == 1){
+//        println(addersSpec.mkString("\n"))
+//        println("------------")
+//      }
 
 
       val revert = useRsUnsignedPlugin generate new Area{

src/main/scala/naxriscv/lsu/DataCache.scala

@@ -1004,7 +1004,7 @@ class DataCache(val p : DataCacheParameters) extends Component {
       val rspWithData = p.withCoherency.mux(io.mem.read.rsp.withData, True)
       if(withCoherency) assert(!(io.mem.read.rsp.valid && !rspWithData && slots.map(_.data).read(io.mem.read.rsp.id)), "Data cache asked for data but didn't recieved any :(")
 
-      val bankWriteNotif = B(0, bankCount bits)
+      val bankWriteNotif = B(0, bankCount bits).allowOverride()
       for ((bank, bankId) <- banks.zipWithIndex) {
         if (!reducedBankWidth) {
           bankWriteNotif(bankId) := io.mem.read.rsp.valid && rspWithData && way === bankId

src/main/scala/naxriscv/misc/RegFilePlugin.scala

@@ -150,15 +150,15 @@ class RegFileLatch(addressWidth    : Int,
 
   val writeFrontend = new Area {
     @dontName val clock = ClockDomain.current.readClockWire
-    val buffers = for (port <- io.writes) yield LatchWhen(port.data, clock)
-//    val buffers = for (port <- io.writes) yield RegNext(port.data)
+//    val buffers = for (port <- io.writes) yield LatchWhen(port.data, clock)
+    val buffers = for (port <- io.writes) yield RegNext(port.data)
   }
 
   val latches = for (i <- headZero.toInt until (1 << addressWidth)/fakeRatio) yield new Area {
     val write = new Area {
       val mask = B(io.writes.map(port => port.valid && port.address === i))
-      val maskReg = LatchWhen(mask, writeFrontend.clock)
-      val validReg = LatchWhen(mask.orR, writeFrontend.clock)
+      val maskReg = RegNext(mask)
+      val validReg = RegNext(mask.orR)
       val data = OhMux.or(maskReg, writeFrontend.buffers)
       val sample = !writeFrontend.clock && validReg
     }

src/main/scala/naxriscv/platform/asic/NaxAsicGen.scala

@@ -1,41 +1,49 @@
 package naxriscv.platform.asic
 
 import naxriscv.{Config, NaxRiscv}
-import naxriscv.compatibility.{EnforceSyncRamPhase, MemReadDuringWriteHazardPhase, MemReadDuringWritePatcherPhase, MultiPortWritesSymplifier}
+import naxriscv.compatibility.{CombRamBlackboxer, EnforceSyncRamPhase, MemReadDuringWriteHazardPhase, MemReadDuringWritePatcherPhase, MultiPortWritesSymplifier}
 import naxriscv.debug.EmbeddedJtagPlugin
 import naxriscv.fetch.FetchCachePlugin
 import naxriscv.lsu.DataCachePlugin
+import naxriscv.lsu2.Lsu2Plugin
 import naxriscv.prediction.{BtbPlugin, GSharePlugin}
 import naxriscv.utilities.DocPlugin
 import spinal.core._
 import spinal.lib._
 import spinal.lib.eda.bench.Rtl
 
 object NaxAsicGen extends App{
-  var target = "asic"
+  var ramBlocks = "inferred"
   var regFileFakeRatio = 1
   var withLsu = true
+  var withIoFf = false
+  var withRfLatchRam = true
+  var blackBoxCombRam = false
 
   assert(new scopt.OptionParser[Unit]("NaxAsicGen") {
     help("help").text("prints this usage text")
-    opt[Unit]("sky130") action { (v, c) => target = "sky130" }
+    opt[Unit]("sky130-ram") action { (v, c) => ramBlocks = "sky130" }
     opt[Int]("regfile-fake-ratio") action { (v, c) => regFileFakeRatio = v }
     opt[Unit]("no-lsu") action { (v, c) => withLsu = false }
+    opt[Unit]("io-ff") action { (v, c) => withIoFf = true }
+    opt[Unit]("no-rf-latch-ram") action { (v, c) => withRfLatchRam = false }
+    opt[Unit]("bb-comb-ram") action { (v, c) => blackBoxCombRam = true }
   }.parse(args, Unit).nonEmpty)
 
 
   LutInputs.set(4)
   def plugins = {
     val l = Config.plugins(
       asic = true,
+      withRfLatchRam = withRfLatchRam,
       withRdTime = false,
       aluCount    = 1,
       decodeCount = 1,
       debugTriggers = 4,
       withDedicatedLoadAgu = false,
       withRvc = false,
       withLoadStore = withLsu,
-      withMmu = false,
+      withMmu = withLsu,
       withDebug = false,
       withEmbeddedJtagTap = false,
       jtagTunneled = false,
@@ -47,6 +55,7 @@ object NaxAsicGen extends App{
       dispatchSlots = 8,
       robSize = 16,
       branchCount = 4,
+      mmuSets = 4,
       regFileFakeRatio = regFileFakeRatio,
       //      withCoherency = true,
       ioRange = a => a(31 downto 28) === 0x1// || !a(12)//(a(5, 6 bits) ^ a(12, 6 bits)) === 51
@@ -57,31 +66,36 @@ object NaxAsicGen extends App{
       case _ =>
     }
 
-    target match {
-      case "asic" => l.foreach {
+    ramBlocks match {
+      case "inferred" => l.foreach {
         case p: FetchCachePlugin => p.wayCount = 1; p.cacheSize = 256; p.memDataWidth = 64
         case p: DataCachePlugin => p.wayCount = 1; p.cacheSize = 256; p.memDataWidth = 64
         case p: BtbPlugin => p.entries = 8
         case p: GSharePlugin => p.memBytes = 32
+        case p: Lsu2Plugin => p.hitPedictionEntries = 64
         case _ =>
       }
       case "sky130" => l.foreach {
         case p: FetchCachePlugin => p.wayCount = 2; p.cacheSize = 4096; p.memDataWidth = 64
         case p: DataCachePlugin => p.wayCount = 2; p.cacheSize = 4096; p.memDataWidth = 64
         case p: BtbPlugin => p.entries = 64
         case p: GSharePlugin => p.memBytes = 512
+        case p: Lsu2Plugin => p.hitPedictionEntries = 64
         case _ =>
       }
     }
     l
   }
 
-  var spinalConfig = target match {
-    case "asic" => SpinalConfig()
+  var spinalConfig = ramBlocks match {
+    case "inferred" => SpinalConfig()
     case "sky130" => SpinalSky130()
   }
 
-  spinalConfig.generateVerilog(new NaxRiscv(plugins).setDefinitionName("nax"))
+  if(blackBoxCombRam) spinalConfig.memBlackBoxers += new CombRamBlackboxer()
+
+  def gen = new NaxRiscv(plugins).setDefinitionName("nax")
+  spinalConfig.generateVerilog(if(withIoFf) Rtl.ffIo(gen) else gen)
 
 //  spinalConfig.generateVerilog(new StreamFifo(UInt(4 bits), 256).setDefinitionName("nax"))
 }

src/main/scala/naxriscv/platform/asic/Sky130.scala

@@ -17,7 +17,7 @@ object SpinalSky130{
   }
   def apply() = {
     val c = SpinalConfig(mode = Verilog)
-    c.addTransformationPhase(new MultiPortWritesSymplifier)
+//    c.addTransformationPhase(new MultiPortWritesSymplifier)
     c.addStandardMemBlackboxing(blackboxPolicy)
     c.phasesInserters += { phases =>
       val i = phases.lastIndexWhere(_.isInstanceOf[PhaseMemBlackBoxingWithPolicy])