Merge pull request #85 from Bill94l/main

Fix wrong mask for 64 bits IO access
SpinalHDL · Mar 6, 2024 · 646cc0f · 646cc0f
2 parents 8f0bd88 + 9d1eb83
commit 646cc0f
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/src/main/scala/naxriscv/platform/NaxriscvProbe.scala b/src/main/scala/naxriscv/platform/NaxriscvProbe.scala
@@ -263,8 +263,8 @@ class NaxriscvProbe(nax : NaxRiscv, hartId : Int){
       ioAccess.error = ioBus.rsp.error.toBoolean
       if(!ioAccess.write) {
         val offset = (ioAccess.address) & (ioBus.p.dataWidth/8-1)
-        val mask = (1l << ioAccess.size*8)-1
-        ioAccess.data = (ioBus.rsp.data.toLong >> offset*8) & mask
+        val mask = (BigInt(1) << ioAccess.size*8)-1
+        ioAccess.data = (ioBus.rsp.data.toLong >> offset*8) & mask.toLong
       }
       backends.foreach(_.ioAccess(hartId, ioAccess))
       ioAccess = null