DIOT version ready for review

Issue #83
sinara-hw · Oct 3, 2024 · 29020e7 · 29020e7
1 parent 26aa02a
commit 29020e7
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Showing 12 changed files with 955 additions and 156 deletions.
diff --git a/PCB/CLK_INPUT.SchDoc b/PCB/CLK_INPUT.SchDoc
diff --git a/PCB/Supply_DDS.SchDoc b/PCB/Supply_DDS.SchDoc
diff --git a/PCB/Urukul.PcbDoc b/PCB/Urukul.PcbDoc
diff --git a/PCB/Urukul.PrjPCB b/PCB/Urukul.PrjPCB
diff --git a/PCB/Urukul.PrjPCBStructure b/PCB/Urukul.PrjPCBStructure
@@ -1,6 +1,5 @@
 Record=TopLevelDocument|FileName=Urukul.schdoc|SheetNumber=1
 Record=SheetSymbol|SourceDocument=Urukul.schdoc|Designator=U_CLK_INPUT|SchDesignator=U_CLK_INPUT|FileName=CLK_INPUT.SchDoc|SheetNumber=6|SymbolType=Normal|RawFileName=CLK_INPUT.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
-Record=SheetSymbol|SourceDocument=Urukul.schdoc|Designator=U_CTRL_LOGIC|SchDesignator=U_CTRL_LOGIC|FileName=CTRL_LOGIC.SchDoc|SheetNumber=7|SymbolType=Normal|RawFileName=CTRL_LOGIC.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
 Record=SheetSymbol|SourceDocument=Urukul.schdoc|Designator=U_DDS_channel0|SchDesignator=U_DDS_channel0|FileName=DDS_channel.SchDoc|SheetNumber=5|SymbolType=Normal|RawFileName=DDS_channel.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
 Record=SheetSymbol|SourceDocument=Urukul.schdoc|Designator=U_DDS_channel1|SchDesignator=U_DDS_channel1|FileName=DDS_channel.SchDoc|SheetNumber=5|SymbolType=Normal|RawFileName=DDS_channel.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
 Record=SheetSymbol|SourceDocument=Urukul.schdoc|Designator=U_DDS_channel2|SchDesignator=U_DDS_channel2|FileName=DDS_channel.SchDoc|SheetNumber=5|SymbolType=Normal|RawFileName=DDS_channel.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
@@ -9,6 +8,9 @@ Record=SheetSymbol|SourceDocument=Urukul.schdoc|Designator=U_DDS_OUT_channel0|Sc
 Record=SheetSymbol|SourceDocument=Urukul.schdoc|Designator=U_DDS_OUT_channel1|SchDesignator=U_DDS_OUT_channel1|FileName=DDS_OUT_channel.SchDoc|SheetNumber=4|SymbolType=Normal|RawFileName=DDS_OUT_channel.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
 Record=SheetSymbol|SourceDocument=Urukul.schdoc|Designator=U_DDS_OUT_channel2|SchDesignator=U_DDS_OUT_channel2|FileName=DDS_OUT_channel.SchDoc|SheetNumber=4|SymbolType=Normal|RawFileName=DDS_OUT_channel.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
 Record=SheetSymbol|SourceDocument=Urukul.schdoc|Designator=U_DDS_OUT_channel3|SchDesignator=U_DDS_OUT_channel3|FileName=DDS_OUT_channel.SchDoc|SheetNumber=4|SymbolType=Normal|RawFileName=DDS_OUT_channel.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
-Record=SheetSymbol|SourceDocument=Urukul.schdoc|Designator=U_LVDS_IFCA|SchDesignator=U_LVDS_IFCA|FileName=LVDS_IFC_DDS.SchDoc|SheetNumber=2|SymbolType=Normal|RawFileName=LVDS_IFC_DDS.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
-Record=SheetSymbol|SourceDocument=Urukul.schdoc|Designator=U_LVDS_IFCB|SchDesignator=U_LVDS_IFCB|FileName=LVDS_IFC_DDS.SchDoc|SheetNumber=2|SymbolType=Normal|RawFileName=LVDS_IFC_DDS.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
-Record=SheetSymbol|SourceDocument=Urukul.schdoc|Designator=U_Supply_DDS|SchDesignator=U_Supply_DDS|FileName=Supply_DDS.SchDoc|SheetNumber=3|SymbolType=Normal|RawFileName=Supply_DDS.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=Urukul.schdoc|Designator=U_Urukul_DIOT_Connectors_P1_P6|SchDesignator=U_Urukul_DIOT_Connectors_P1_P6|FileName=Urukul_DIOT_Connectors_P1_P6.SchDoc|SheetNumber=11|SymbolType=Normal|RawFileName=Urukul_DIOT_Connectors_P1_P6.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=Urukul.schdoc|Designator=U_Urukul_FPGA|SchDesignator=U_Urukul_FPGA|FileName=Urukul_FPGA.SchDoc|SheetNumber=4|SymbolType=Normal|RawFileName=Urukul_FPGA.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=Urukul.schdoc|Designator=U_Urukul_FPGA_Config|SchDesignator=U_Urukul_FPGA_Config|FileName=Urukul_FPGA_Config.SchDoc|SheetNumber=7|SymbolType=Normal|RawFileName=Urukul_FPGA_Config.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=Urukul.schdoc|Designator=U_Urukul_FPGA_LVDS|SchDesignator=U_Urukul_FPGA_LVDS|FileName=Urukul_FPGA_LVDS.SchDoc|SheetNumber=5|SymbolType=Normal|RawFileName=Urukul_FPGA_LVDS.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=Urukul.schdoc|Designator=U_Urukul_FPGA_Supply|SchDesignator=U_Urukul_FPGA_Supply|FileName=Urukul_FPGA_Supply.SchDoc|SheetNumber=9|SymbolType=Normal|RawFileName=Urukul_FPGA_Supply.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=Urukul.schdoc|Designator=U_Urukul_Supply|SchDesignator=U_Urukul_Supply|FileName=Urukul_Supply.SchDoc|SheetNumber=3|SymbolType=Normal|RawFileName=Urukul_Supply.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
diff --git a/PCB/Urukul.schdoc b/PCB/Urukul.schdoc
diff --git a/PCB/Urukul_DIOT_Connectors_P1_P6.SchDoc b/PCB/Urukul_DIOT_Connectors_P1_P6.SchDoc
diff --git a/PCB/Urukul_FPGA.SchDoc b/PCB/Urukul_FPGA.SchDoc
diff --git a/PCB/Urukul_FPGA_Config.SchDoc b/PCB/Urukul_FPGA_Config.SchDoc
diff --git a/PCB/Urukul_FPGA_LVDS.SchDoc b/PCB/Urukul_FPGA_LVDS.SchDoc
diff --git a/PCB/Urukul_FPGA_Supply.SchDoc b/PCB/Urukul_FPGA_Supply.SchDoc
diff --git a/PCB/Urukul_Supply.SchDoc b/PCB/Urukul_Supply.SchDoc