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Various bug fixes and cleanup #212

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merged 8 commits into from
Oct 15, 2024
Merged

Various bug fixes and cleanup #212

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4d3c8c7
Fixed Dispatch stats; added a couple of tests
klingaard Sep 27, 2024
02ee83a
New testcases; added Issue PEvent
knute-mips Sep 28, 2024
7be1479
Merge remote-tracking branch 'origin/master' into klingaard/various_b…
klingaard Sep 29, 2024
8074995
Added rename of pipes for clarity
klingaard Sep 29, 2024
bb3c771
Fixed layout files
klingaard Sep 29, 2024
e33aefd
Align the addr in the testcase
klingaard Sep 29, 2024
4f40f82
Fixed dcache hit timing issue with LS
klingaard Oct 6, 2024
c14c03b
Updated EXPECTED files with new whitespace and DCache behavior
klingaard Oct 8, 2024
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20 changes: 18 additions & 2 deletions arches/big_core.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -40,18 +40,34 @@ top.cpu.core0.extension.core_extensions:
# ["0", "3"] means iq0 has exe0, exe1, exe2, and exe3, so it's inclusive
# if you want just one execution unit to issue queue you can do:
# ["0"] which would result in iq0 -> exe0
# *note if you change the number of issue queues,
# *note if you change the number of issue queues,
# you need to add it to latency matrix below

issue_queue_to_pipe_map:
[
[
["0", "1"], # iq0 -> exe0, exe1
["2", "3"], # iq1 -> exe2, exe3
["4", "5"], # iq2 -> exe4, exe5
["6", "7"], # iq3 -> exe6, exe7
["8", "9"], # iq4 -> exe8, exe9
["10"] # iq5 -> exe10
]

exe_pipe_rename:
[
["exe0", "sys_pipe"],
["exe1", "alu1_pipe"],
["exe2", "alu2_pipe"],
["exe3", "alu3_pipe"],
["exe4", "alu4_pipe"],
["exe5", "alu5_pipe"],
["exe6", "fpu0_pipe"],
["exe7", "fpu1_pipe"],
["exe8", "br0_pipe"],
["exe9", "br1_pipe"],
["exe10", "vint_pipe"]
]

top.cpu.core0.rename.scoreboards:
# From
# |
Expand Down
17 changes: 14 additions & 3 deletions arches/medium_core.yaml
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Expand Up @@ -29,22 +29,33 @@ top.cpu.core0.extension.core_extensions:
["br"], # exe5
["vint", "vset", "vdiv", "vmul"] # exe6
]

# this is used to set how many units per queue
# ["0", "3"] means iq0 has exe0, exe1, exe2, and exe3, so it's inclusive
# if you want just one execution unit to issue queue you can do:
# ["0"] which would result in iq0 -> exe0
# *note if you change the number of issue queues,
# *note if you change the number of issue queues,
# you need to add it to latency matrix below
issue_queue_to_pipe_map:
[
[
["0"], # iq0 -> exe0
["1", "2"], # iq1 -> exe1, exe2
["3", "4"], # iq2 -> exe3, exe4
["5"], # iq3 -> exe5
["6"]
]

exe_pipe_rename:
[
["exe0", "alu0_pipe"],
["exe1", "alu1_pipe"],
["exe2", "alu2_pipe"],
["exe3", "fpu0_pipe"],
["exe4", "fpu1_pipe"],
["exe5", "br_pipe"],
["exe6", "vint_pipe"]
]

top.cpu.core0.rename.scoreboards:
# From
# |
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13 changes: 11 additions & 2 deletions arches/small_core.yaml
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Expand Up @@ -27,16 +27,25 @@ top.cpu.core0.extension.core_extensions:
# ["0", "3"] means iq0 has exe0, exe1, exe2, and exe3, so it's inclusive
# if you want just one execution unit to issue queue you can do:
# ["0"] which would result in iq0 -> exe0
# *note if you change the number of issue queues,
# *note if you change the number of issue queues,
# you need to add it to latency matrix below
issue_queue_to_pipe_map:
[
[
["0"], # iq0 -> exe0
["1"], # iq1 -> exe1
["2"], # iq2 -> exe2
["3"], # iq3 -> exe3
]

exe_pipe_rename:
[
["exe0", "alu0_pipe"],
["exe1", "fpu0_pipe"],
["exe2", "br_pipe"],
["exe3", "vint_pipe"]
]


top.cpu.core0.rename.scoreboards:
# From
# |
Expand Down
1 change: 0 additions & 1 deletion core/DCache.cpp
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Expand Up @@ -272,7 +272,6 @@ namespace olympia
void DCache::receiveMemReqFromLSU_(const MemoryAccessInfoPtr & memory_access_info_ptr)
{
ILOG("Received memory access request from LSU " << memory_access_info_ptr);
out_lsu_lookup_ack_.send(memory_access_info_ptr);
in_l2_cache_resp_receive_event_.schedule();
lsu_mem_access_info_ = memory_access_info_ptr;
}
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2 changes: 1 addition & 1 deletion core/DCache.hpp
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Expand Up @@ -97,7 +97,7 @@ namespace olympia
// Input Ports
////////////////////////////////////////////////////////////////////////////////
sparta::DataInPort<MemoryAccessInfoPtr> in_lsu_lookup_req_{&unit_port_set_,
"in_lsu_lookup_req", 1};
"in_lsu_lookup_req", 0};

sparta::DataInPort<uint32_t> in_l2cache_ack_{&unit_port_set_, "in_l2cache_ack", 1};

Expand Down
148 changes: 77 additions & 71 deletions core/Dispatch.hpp
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Expand Up @@ -153,83 +153,89 @@ namespace olympia
// Counters -- this is only supported in C++11 -- uses
// Counter's move semantics
std::array<sparta::CycleCounter, N_STALL_REASONS> stall_counters_{
{sparta::CycleCounter(getStatisticSet(), "stall_cmov_busy", "CMOV busy",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_div_busy", "DIV busy",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_faddsub_busy", "FADDSUB busy",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_float_busy", "FLOAT busy",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_fmac_busy", "FMAC busy",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_i2f_busy", "I2F busy",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_f2i_busy", "F2I busy",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_int_busy", "INT busy",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_lsu_busy", "LSU busy",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_mul_busy", "MUL busy",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_br_busy", "BR busy",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_vint_busy", "VINT busy",
sparta::Counter::COUNT_NORMAL, getClock()),
{
sparta::CycleCounter(getStatisticSet(), "stall_br_busy", "BR busy",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_cmov_busy", "CMOV busy",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_div_busy", "DIV busy",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_faddsub_busy", "FADDSUB busy",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_float_busy", "FLOAT busy",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_fmac_busy", "FMAC busy",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_i2f_busy", "I2F busy",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_f2i_busy", "F2I busy",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_int_busy", "INT busy",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_lsu_busy", "LSU busy",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_mul_busy", "MUL busy",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_vint_busy", "VINT busy",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_vfixed_busy", "VFIXED busy",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_vmask_busy", "VMASK busy",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_vmul_busy", "VMUL busy",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_vdiv_busy", "VDIV busy",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_vset_busy", "VSET busy",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_sys_busy", "No credits from ROB",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_not_stalled",
"Dispatch not stalled, all instructions dispatched",
sparta::Counter::COUNT_NORMAL, getClock())}};
sparta::CycleCounter(getStatisticSet(), "stall_vmask_busy", "VMASK busy",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_vmul_busy", "VMUL busy",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_vdiv_busy", "VDIV busy",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_vset_busy", "VSET busy",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_rob_full", "No credits from ROB",
sparta::Counter::COUNT_NORMAL, getClock()),
sparta::CycleCounter(getStatisticSet(), "stall_not_stalled",
"Dispatch not stalled, all instructions dispatched",
sparta::Counter::COUNT_NORMAL, getClock())
}
};

std::array<sparta::Counter, InstArchInfo::N_TARGET_PIPES> unit_distribution_{
{sparta::Counter(getStatisticSet(), "count_cmov_insts", "Total CMOV insts",
sparta::Counter::COUNT_NORMAL),
sparta::Counter(getStatisticSet(), "count_div_insts", "Total DIV insts",
sparta::Counter::COUNT_NORMAL),
sparta::Counter(getStatisticSet(), "count_faddsub_insts", "Total FADDSUB insts",
sparta::Counter::COUNT_NORMAL),
sparta::Counter(getStatisticSet(), "count_float_insts", "Total FLOAT insts",
sparta::Counter::COUNT_NORMAL),
sparta::Counter(getStatisticSet(), "count_fmac_insts", "Total FMAC insts",
sparta::Counter::COUNT_NORMAL),
sparta::Counter(getStatisticSet(), "count_i2f_insts", "Total I2F insts",
sparta::Counter::COUNT_NORMAL),
sparta::Counter(getStatisticSet(), "count_f2i_insts", "Total F2I insts",
sparta::Counter::COUNT_NORMAL),
sparta::Counter(getStatisticSet(), "count_int_insts", "Total INT insts",
sparta::Counter::COUNT_NORMAL),
sparta::Counter(getStatisticSet(), "count_lsu_insts", "Total LSU insts",
sparta::Counter::COUNT_NORMAL),
sparta::Counter(getStatisticSet(), "count_mul_insts", "Total MUL insts",
sparta::Counter::COUNT_NORMAL),
sparta::Counter(getStatisticSet(), "count_br_insts", "Total BR insts",
sparta::Counter::COUNT_NORMAL),
sparta::Counter(getStatisticSet(), "count_vint_insts", "Total VINT insts",
{
sparta::Counter(getStatisticSet(), "count_br_insts", "Total BR insts",
sparta::Counter::COUNT_NORMAL),
sparta::Counter(getStatisticSet(), "count_cmov_insts", "Total CMOV insts",
sparta::Counter::COUNT_NORMAL),
sparta::Counter(getStatisticSet(), "count_div_insts", "Total DIV insts",
sparta::Counter::COUNT_NORMAL),
sparta::Counter(getStatisticSet(), "count_faddsub_insts", "Total FADDSUB insts",
sparta::Counter::COUNT_NORMAL),
sparta::Counter(getStatisticSet(), "count_float_insts", "Total FLOAT insts",
sparta::Counter::COUNT_NORMAL),
sparta::Counter(getStatisticSet(), "count_fmac_insts", "Total FMAC insts",
sparta::Counter::COUNT_NORMAL),
sparta::Counter(getStatisticSet(), "count_i2f_insts", "Total I2F insts",
sparta::Counter::COUNT_NORMAL),
sparta::Counter(getStatisticSet(), "count_f2i_insts", "Total F2I insts",
sparta::Counter::COUNT_NORMAL),
sparta::Counter(getStatisticSet(), "count_int_insts", "Total INT insts",
sparta::Counter::COUNT_NORMAL),
sparta::Counter(getStatisticSet(), "count_lsu_insts", "Total LSU insts",
sparta::Counter::COUNT_NORMAL),
sparta::Counter(getStatisticSet(), "count_mul_insts", "Total MUL insts",
sparta::Counter::COUNT_NORMAL),
sparta::Counter(getStatisticSet(), "count_vint_insts", "Total VINT insts",
sparta::Counter::COUNT_NORMAL),
sparta::Counter(getStatisticSet(), "count_vfixed_insts", "Total VFIXED insts",
sparta::Counter::COUNT_NORMAL),
sparta::Counter(getStatisticSet(), "count_vmask_insts", "Total VMASK insts",
sparta::Counter::COUNT_NORMAL),
sparta::Counter(getStatisticSet(), "count_vmul_insts", "Total VMUL insts",
sparta::Counter::COUNT_NORMAL),
sparta::Counter(getStatisticSet(), "count_vdiv_insts", "Total VDIV insts",
sparta::Counter::COUNT_NORMAL),
sparta::Counter(getStatisticSet(), "count_vset_insts", "Total VSET insts",
sparta::Counter::COUNT_NORMAL),
sparta::Counter(getStatisticSet(), "count_sys_insts", "Total SYS insts",
sparta::Counter::COUNT_NORMAL)}};
sparta::Counter::COUNT_NORMAL),
sparta::Counter(getStatisticSet(), "count_vmask_insts", "Total VMASK insts",
sparta::Counter::COUNT_NORMAL),
sparta::Counter(getStatisticSet(), "count_vmul_insts", "Total VMUL insts",
sparta::Counter::COUNT_NORMAL),
sparta::Counter(getStatisticSet(), "count_vdiv_insts", "Total VDIV insts",
sparta::Counter::COUNT_NORMAL),
sparta::Counter(getStatisticSet(), "count_vset_insts", "Total VSET insts",
sparta::Counter::COUNT_NORMAL),
sparta::Counter(getStatisticSet(), "count_sys_insts", "Total SYS insts",
sparta::Counter::COUNT_NORMAL)
}
};

// As an example, this is a context counter that does the same
// thing as the unit_distribution counter, albeit a little
Expand Down
6 changes: 3 additions & 3 deletions core/Inst.hpp
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Expand Up @@ -517,9 +517,9 @@ namespace olympia
// - any changes here will break EXPECT
inline std::ostream & operator<<(std::ostream & os, const Inst & inst)
{
os << "uid: " << inst.getUniqueID() << " " << std::setw(10) << inst.getStatus() << " "
<< std::hex << inst.getPC() << std::dec << " pid: " << inst.getProgramID()
<< " uopid: " << inst.getUOpID() << " '" << inst.getDisasm() << "' ";
os << "uid:" << inst.getUniqueID() << std::setw(10) << inst.getStatus() << " "
<< std::hex << inst.getPC() << std::dec << " pid:" << inst.getProgramID()
<< " uopid:" << inst.getUOpID() << " '" << inst.getDisasm() << "' ";
return os;
}

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1 change: 1 addition & 0 deletions core/IssueQueue.cpp
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Expand Up @@ -188,6 +188,7 @@ namespace olympia
ready_queue_.erase(delete_iter);
popIssueQueue_(inst);
++total_insts_issued_;
issue_event_.collect(*inst);
break;
}
}
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7 changes: 6 additions & 1 deletion core/IssueQueue.hpp
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Expand Up @@ -14,6 +14,7 @@
#include "sparta/simulation/ResourceFactory.hpp"
#include "sparta/simulation/TreeNode.hpp"
#include "sparta/simulation/Unit.hpp"
#include "sparta/pevents/PeventCollector.hpp"

#include "sparta/resources/PriorityQueue.hpp"

Expand Down Expand Up @@ -137,9 +138,13 @@ namespace olympia
sparta::Counter::COUNT_NORMAL};
bool rob_stopped_simulation_ = false;
friend class IssueQueueTester;

// For correlation activities
sparta::pevents::PeventCollector<InstPEventPairs> issue_event_{"ISSUE", getContainer(), getClock()};

};

using IssueQueueFactory =
sparta::ResourceFactory<olympia::IssueQueue, olympia::IssueQueue::IssueQueueParameterSet>;
class IssueQueueTester;
} // namespace olympia
} // namespace olympia
9 changes: 8 additions & 1 deletion core/LSU.cpp
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Expand Up @@ -104,6 +104,12 @@ namespace olympia
node->getParent()->registerForNotification<bool, LSU, &LSU::onROBTerminate_>(
this, "rob_stopped_notif_channel", false /* ROB maybe not be constructed yet */);


auto & events = ldst_pipeline_.getEventsAtStage(cache_read_stage_);
for (auto & event : events) {
in_cache_lookup_ack_.registerConsumerEvent(event->getScheduleable());
}

uev_append_ready_ >> uev_issue_inst_;
// NOTE:
// To resolve the race condition when:
Expand Down Expand Up @@ -244,7 +250,7 @@ namespace olympia
// either a new issue event, or a re-issue event
// however, we can ONLY update instruction status as SCHEDULED for a new issue event

ILOG("Another issue event scheduled " << inst_ptr);
ILOG("Inst fully readdy: " << inst_ptr);

if (isReadyToIssueInsts_())
{
Expand Down Expand Up @@ -529,6 +535,7 @@ namespace olympia
// Is its a cache miss we dont need to rechedule the instruction
if (!mem_access_info_ptr->isCacheHit())
{
ILOG("ma cache miss: " << mem_access_info_ptr);
return;
}

Expand Down
4 changes: 2 additions & 2 deletions core/LoadStoreInstInfo.hpp
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Expand Up @@ -195,8 +195,8 @@ namespace olympia
inline std::ostream & operator<<(std::ostream & os, const olympia::LoadStoreInstInfo & ls_info)
{
os << "lsinfo: "
<< "uid: " << ls_info.getInstUniqueID() << " pri:" << ls_info.getPriority()
<< " state: " << ls_info.getState();
<< "uid:" << ls_info.getInstUniqueID() << " pri:" << ls_info.getPriority()
<< " state:" << ls_info.getState();
return os;
}

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4 changes: 2 additions & 2 deletions layouts/Makefile
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@@ -1,9 +1,9 @@

all: small_core.alf medium_core.alf big_core.alf

%_core.alf: ./gen_alf.py
%_core.alf: ./gen_alf.py ../fastdebug/olympia
@echo "Generating pipeout for $@"
@(cd ../release; ./olympia -z ../layouts/pipeout -i1 traces/dhry_riscv.zstf > /dev/null)
@(cd ../fastdebug; ./olympia -z ../layouts/pipeout -i1 traces/dhry_riscv.zstf > /dev/null)
@./gen_alf.py -d pipeoutlocation.dat -a $*_core.alf
@rm pipeout*

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