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Add uvm environment #15

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merged 38 commits into from
Mar 5, 2024
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096c2aa
Update Add uvm env
M0stafaRady Jan 12, 2024
145d114
Correct format of logger table
M0stafaRady Jan 14, 2024
9e578e4
fix uart test
M0stafaRady Jan 14, 2024
7236204
rx and tx are verified
M0stafaRady Jan 16, 2024
961f7ed
Add documentation
M0stafaRady Jan 17, 2024
ac8d928
Add checker for parity and data bits vary length
M0stafaRady Jan 21, 2024
0dc2aae
Add loop back and glitch filter verification support
M0stafaRady Jan 23, 2024
1c1fba6
Add irq to uvm env
M0stafaRady Jan 24, 2024
1105bc6
update config function to take more arguments
M0stafaRady Jan 28, 2024
ad0cbb0
update irqs and add coverage and sequences for ip
M0stafaRady Jan 31, 2024
da30b76
update makefile and tests
M0stafaRady Feb 4, 2024
dc3111d
move sequences under ip
M0stafaRady Feb 4, 2024
02bd2b2
move env to another repo
M0stafaRady Feb 4, 2024
542e8a4
update make file
M0stafaRady Feb 4, 2024
531871a
Add logic to disable functional coverage and generate wave
M0stafaRady Feb 5, 2024
9941769
Merge pull request #13 from efabless/main
M0stafaRady Feb 19, 2024
b8b94fe
changes made because the yaml file is changed
M0stafaRady Feb 19, 2024
e768ecb
update make file to clone ef_uvm
M0stafaRady Feb 19, 2024
a88be1e
Add CI (#14)
M0stafaRady Feb 20, 2024
eb85d17
Merge branch 'main' into uvm
M0stafaRady Feb 25, 2024
b7a72fc
update make file with ip_utilities for uvm verification
M0stafaRady Feb 25, 2024
a289e47
fix syntax error and some wrong variables sizes
M0stafaRady Feb 25, 2024
fed3475
Add all tests to test list
M0stafaRady Feb 25, 2024
230420d
Add enable port to the filter
M0stafaRady Feb 26, 2024
01594d0
Add supoort to verify ahb
M0stafaRady Feb 28, 2024
96b2a26
Change url for EF_UVM as the owner of the repo changed to efabless
M0stafaRady Feb 28, 2024
3e848ab
update CI to upload failed results, inject error in monitor to try CI
M0stafaRady Feb 29, 2024
4e5e4ef
fix syntax error in CI
M0stafaRady Feb 29, 2024
9cb5c5c
fix syntax error in CI
M0stafaRady Feb 29, 2024
49e252a
revert error injected to make the CI fail
M0stafaRady Feb 29, 2024
b97ecba
Add linting to CI
M0stafaRady Feb 29, 2024
da7f96c
Add linting to CI
M0stafaRady Feb 29, 2024
e6338d3
Add linting to CI
M0stafaRady Feb 29, 2024
56fb702
Add linting to CI
M0stafaRady Feb 29, 2024
123a6f2
Add linting to CI
M0stafaRady Feb 29, 2024
9e8cc40
Add support for wishbone
M0stafaRady Feb 29, 2024
524d839
add AHB verification to the CI
M0stafaRady Feb 29, 2024
d5f04b7
change name of wrapper to bus
M0stafaRady Mar 5, 2024
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144 changes: 144 additions & 0 deletions .github/workflows/uvm_ci.yaml
Original file line number Diff line number Diff line change
@@ -0,0 +1,144 @@
name: Run UVM all tests

on:
push: # This now triggers on pushes to any branch
pull_request: # This now triggers on pull requests to any branch

jobs:
verify_APB:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2

- name: Set up Python
uses: actions/setup-python@v2
with:
python-version: '3.x'

- name: download docker
run: |
docker pull efabless/dv:cocotb

- name: Navigate to verify/uvm-python and run tests
run: |
cd verify/uvm-python
make run_all_tests RUN_MERGE_COVERAGE=false

- name: Check for test results in run
run: |
cd verify/uvm-python
passed_count=$(find sim/default_tag -type f -name 'passed' | wc -l)
failed_count=$(find sim/default_tag -type f -name 'failed' | wc -l)
unknown_count=$(find sim/default_tag -type f -name 'unknown' | wc -l)

echo "Passed: $passed_count"
echo "Failed: $failed_count"
echo "Unknown: $unknown_count"

if [ "$passed_count" -eq 0 ]; then
echo "Error: No passed test results found"
exit 1
elif [ "$failed_count" -ne 0 ] || [ "$unknown_count" -ne 0 ]; then
echo "Error: There are failed or unknown test results"
exit 1
else
echo "All tests passed successfully"
fi
- name: tar failed tests
if: failure()
run: |
cd verify/uvm-python
tar -czf failed_tests.tar.gz sim/default_tag

- name: upload failed tests
if: failure()
uses: actions/upload-artifact@v2
with:
name: failed_tests
path: verify/uvm-python/failed_tests.tar.gz

verify_AHB:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2

- name: Set up Python
uses: actions/setup-python@v2
with:
python-version: '3.x'

- name: download docker
run: |
docker pull efabless/dv:cocotb

- name: Navigate to verify/uvm-python and run tests
run: |
cd verify/uvm-python
make run_all_tests RUN_MERGE_COVERAGE=false BUS_TYPE=AHB

- name: Check for test results in run
run: |
cd verify/uvm-python
passed_count=$(find sim/default_tag -type f -name 'passed' | wc -l)
failed_count=$(find sim/default_tag -type f -name 'failed' | wc -l)
unknown_count=$(find sim/default_tag -type f -name 'unknown' | wc -l)

echo "Passed: $passed_count"
echo "Failed: $failed_count"
echo "Unknown: $unknown_count"

if [ "$passed_count" -eq 0 ]; then
echo "Error: No passed test results found"
exit 1
elif [ "$failed_count" -ne 0 ] || [ "$unknown_count" -ne 0 ]; then
echo "Error: There are failed or unknown test results"
exit 1
else
echo "All tests passed successfully"
fi
- name: tar failed tests
if: failure()
run: |
cd verify/uvm-python
tar -czf failed_tests.tar.gz sim/default_tag

- name: upload failed tests
if: failure()
uses: actions/upload-artifact@v2
with:
name: failed_tests
path: verify/uvm-python/failed_tests.tar.gz

lint: # Lint the RTL code
runs-on: ubuntu-latest
steps:
- name: Set up Python
uses: actions/setup-python@v2
with:
python-version: '3.x'

- name: download docker
run: |
docker pull efabless/dv:cocotb

- uses: actions/checkout@v2
- name: Lint
run: |
cd verify/uvm-python
make lint BUS_TYPE=APB
cnt=$(grep -c "Error" "sim/linter.log")
if ! [[ $cnt ]]; then cnt=0; fi
if [[ $cnt -eq 1 ]]; then exit 0; fi
exit 2
cnt=$(grep -c "Warning" "sim/linter.log")
if ! [[ $cnt ]]; then cnt=0; fi
if [[ $cnt -eq 1 ]]; then exit 0; fi
exit 2
- name: Upload lint results
if: failure()
uses: actions/upload-artifact@v2
with:
name: lint_results.log
path: verify/uvm-python/sim/linter.log


10 changes: 6 additions & 4 deletions hdl/rtl/EF_UART.v
Original file line number Diff line number Diff line change
Expand Up @@ -110,6 +110,7 @@ module EF_UART #(parameter MDW = 9, // Max data size/width
aucohl_glitch_filter #(.N(GFLEN)) rx_glitch_filter (
.clk(clk),
.rst_n(rst_n),
.en(glitch_filter_en),
.in(rx_synched),
.out(rx_filtered)
);
Expand Down Expand Up @@ -266,7 +267,7 @@ module UART_RX #(parameter NUM_SAMPLES = 16, MDW = 8)(
reg [3:0] b_reg; //baud-rate/over sampling counter
reg [3:0] b_next;
reg [3:0] count_reg; //data-bit counter
reg [2:0] count_next;
reg [3:0] count_next;
reg [8:0] data_reg; //data register
reg [8:0] data_next;
reg p_error_reg;
Expand Down Expand Up @@ -308,6 +309,7 @@ module UART_RX #(parameter NUM_SAMPLES = 16, MDW = 8)(
data_next = data_reg;
rx_done = 1'b0;
p_error_next = 1'b0;
f_error_next = 1'b0;

case(current_state)
idle_st:
Expand Down Expand Up @@ -441,16 +443,16 @@ module UART_TX #(parameter NUM_SAMPLES = 16, MDW = 8)(
reg [2:0] next_state;
reg [3:0] b_reg; // baud tick counter
reg [3:0] b_next;
reg [2:0] count_reg; // data bit counter
reg [2:0] count_next;
reg [3:0] count_reg; // data bit counter
reg [3:0] count_next;
reg [8:0] data_reg; // data register
reg [8:0] data_next;
reg tx_reg; // output data reg
reg tx_next;

// prepare the data to claculate the parity by removing any extra bits entered
// by the user by error
wire [MDW-1] pdata = (d_in) & ~(MDW'hFF << data_size);
wire [MDW-1] pdata = (d_in) & ~({MDW{1'b1}} << data_size);

//State Machine
always @(posedge clk, negedge resetn) begin
Expand Down
2 changes: 1 addition & 1 deletion hdl/rtl/bus_wrappers/EF_UART_APB.v
Original file line number Diff line number Diff line change
Expand Up @@ -243,7 +243,7 @@ module EF_UART_APB #(
assign PREADY = 1'b1;

assign RXDATA_WIRE = rdata;
assign rd = (apb_re & (PADDR[`APB_AW-1:0] == RXDATA_REG_OFFSET) & PENABLE);
assign rd = (apb_re & (PADDR[`APB_AW-1:0] == RXDATA_REG_OFFSET));
assign wdata = PWDATA;
assign wr = (apb_we & (PADDR[`APB_AW-1:0] == TXDATA_REG_OFFSET));
endmodule
13 changes: 13 additions & 0 deletions verify/uvm-python/.gitignore
Original file line number Diff line number Diff line change
@@ -0,0 +1,13 @@
*.yalm
*.html
*.pyc
*/__pycache__/
*.code-workspace
*.log
*.vcd
/sim/
/coverageReports/
*.xml
*.gtkw
/EF_UVM/
IP_Utilities/
46 changes: 46 additions & 0 deletions verify/uvm-python/Makefile
Original file line number Diff line number Diff line change
@@ -0,0 +1,46 @@
PLUSARGS += "+UVM_VERBOSITY=UVM_HIGH"
TOPLEVEL := top
MODULE ?= top_module
AHB_FILES ?= $(PWD)/../../hdl/rtl/bus_wrappers/EF_UART_AHBL.pp.v
APB_FILES ?= $(PWD)/../../hdl/rtl/bus_wrappers/EF_UART_APB.pp.v
WB_FILES ?= $(PWD)/../../hdl/rtl/bus_wrappers/EF_UART_wb.v
HDL_FILES ?= $(PWD)/IP_Utilities/rtl/aucohl_lib.v $(PWD)/IP_Utilities/rtl/aucohl_rtl.vh $(PWD)/../../hdl/rtl/EF_UART.v
VERILOG_SOURCES ?= $(PWD)/top.v $(AHB_FILES) $(APB_FILES) $(WB_FILES) $(HDL_FILES)
RTL_MACROS += ""
BUS_TYPE ?= APB
ifeq ($(BUS_TYPE),APB)
RTL_MACROS += -DBUS_TYPE_APB
else ifeq ($(BUS_TYPE),AHB)
RTL_MACROS += -DBUS_TYPE_AHB
else ifeq ($(BUS_TYPE),WISHBONE)
RTL_MACROS += -DBUS_TYPE_WISHBONE
endif
# RTL_MACROS ?= "-DSKIP_WAVE_DUMP"
YAML_FILE = $(PWD)/../../EF_UART.yaml
MAKEFLAGS += --no-print-directory

# List of tests
TESTS := TX_StressTest RX_StressTest LoopbackTest PrescalarStressTest LengthParityTXStressTest LengthParityRXStressTest WriteReadRegsTest
# TESTS := TX_StressTest

# Variable for tag - set this as required
SIM_TAG ?= default_tag

# Define SIM_PATH variable
SIM_PATH := $(PWD)/sim/$(SIM_TAG)

# Check and clone EF_UVM repository at the beginning of the Makefile execution

clone_ip_util := $(shell if [ ! -d "IP_Utilities" ]; then \
echo "Cloning the IP_Utilities repository..."; \
git clone https://github.com/shalan/IP_Utilities.git; \
fi;)

clone_ef_uvm := $(shell if [ ! -d "EF_UVM" ]; then \
echo "Cloning the EF_UVM repository..."; \
git clone https://github.com/efabless/EF_UVM.git; \
fi;)



include EF_UVM/Makefile.test
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