fix dir structure and add missing modules

EF_UART.yaml

@@ -16,15 +16,15 @@ info:
     - serial
   bus:
     - generic
-  type": soft
-  status: verified
+  type: soft
+  maturity: implemented
   cell_count:
     - IP: 1590
     - APB: 1943
     - AHBL: 1973
     - WB: 2170
-  width": "0.0"
-  height": "0.0"
+  width: "0.0"
+  height: "0.0"
   technology: n/a
   clock_freq_mhz:
     - IP: 277

hdl/rtl/EF_UART.v

@@ -103,13 +103,13 @@ module EF_UART #(parameter  MDW = 9,        // Max data size/width
     wire        rx_filtered;
     wire        rx_in;
 
-    aucohl_sync rx_sync (
+    sync rx_sync (
         .clk(clk),
         .in(rx),
         .out(rx_synched)
     );
 
-    aucohl_glitch_filter #(.N(GFLEN)) rx_glitch_filter (
+    glitch_filter #(.N(GFLEN)) rx_glitch_filter (
         .clk(clk),
         .rst_n(rst_n),
         .en(glitch_filter_en),
@@ -129,7 +129,7 @@ module EF_UART #(parameter  MDW = 9,        // Max data size/width
         .baudtick(b_tick)
     );
 
-    aucohl_fifo #(.DW(FIFO_DW), .AW(FAW)) fifo_tx (
+    fifo #(.DW(FIFO_DW), .AW(FAW)) fifo_tx (
         .clk(clk),
         .rst_n(rst_n),
         .rd(tx_done),
@@ -155,7 +155,7 @@ module EF_UART #(parameter  MDW = 9,        // Max data size/width
         .tx(tx)
     );
 
-    aucohl_fifo #(.DW(FIFO_DW), .AW(FAW)) fifo_rx (
+    fifo #(.DW(FIFO_DW), .AW(FAW)) fifo_rx (
         .clk(clk),
         .rst_n(rst_n),
         .rd(rd),

hdl/rtl/fifo.v

@@ -0,0 +1,118 @@
+/*
+    A FIFO
+    Depth = 2^AW
+    Width = DW
+*/
+module fifo #(parameter DW=8, AW=4)(
+    input   wire            clk,
+    input   wire            rst_n,
+    input   wire            rd,
+    input   wire            wr,
+    input   wire            flush,
+    input   wire [DW-1:0]   wdata,
+    output  wire            empty,
+    output  wire            full,
+    output  wire [DW-1:0]   rdata,
+    output  wire [AW-1:0]   level    
+);
+
+    localparam  DEPTH = 2**AW;
+
+    //Internal Signal declarations
+    reg [DW-1:0]  array_reg [DEPTH-1:0];
+    reg [AW-1:0]  w_ptr_reg;
+    reg [AW-1:0]  w_ptr_next;
+    reg [AW-1:0]  w_ptr_succ;
+    reg [AW-1:0]  r_ptr_reg;
+    reg [AW-1:0]  r_ptr_next;
+    reg [AW-1:0]  r_ptr_succ;
+
+    // Level
+    reg [AW-1:0] level_reg;
+    reg [AW-1:0] level_next;      
+    reg full_reg;
+    reg empty_reg;
+    reg full_next;
+    reg empty_next;
+
+    wire w_en;
+
+    always @ (posedge clk)
+        if(w_en) begin
+            array_reg[w_ptr_reg] <= wdata;
+        end
+
+    assign rdata = array_reg[r_ptr_reg];   
+    assign w_en = wr & ~full_reg;           
+
+    //State Machine
+    always @ (posedge clk, negedge rst_n) begin 
+        if(!rst_n)
+            begin
+                w_ptr_reg <= 'b0;
+                r_ptr_reg <= 'b0;
+                full_reg  <= 1'b0;
+                empty_reg <= 1'b1;
+                level_reg <= 'd0;
+            end
+        else if(flush)
+            begin
+                w_ptr_reg <= 'b0;
+                r_ptr_reg <= 'b0;
+                full_reg  <= 1'b0;
+                empty_reg <= 1'b1;
+                level_reg <= 'd0;
+            end
+        else
+            begin
+                w_ptr_reg <= w_ptr_next;
+                r_ptr_reg <= r_ptr_next;
+                full_reg  <= full_next;
+                empty_reg <= empty_next;
+                level_reg <= level_next;
+            end
+    end
+
+    //Next State Logic
+    always @* begin
+        w_ptr_succ  =   w_ptr_reg + 1;
+        r_ptr_succ  =   r_ptr_reg + 1;
+        w_ptr_next  =   w_ptr_reg;
+        r_ptr_next  =   r_ptr_reg;
+        full_next   =   full_reg;
+        empty_next  =   empty_reg;
+        level_next  =   level_reg;
+
+        case({w_en,rd})
+            //2'b00: nop
+            2'b01: 
+                if(~empty_reg) begin
+                    r_ptr_next = r_ptr_succ;
+                    full_next = 1'b0;
+                    level_next = level_reg - 1;
+                    if (r_ptr_succ == w_ptr_reg)
+                        empty_next = 1'b1;
+                end
+
+            2'b10: 
+                if(~full_reg) begin
+                    w_ptr_next = w_ptr_succ;
+                    empty_next = 1'b0;
+                    level_next = level_reg + 1;
+                    if (w_ptr_succ == r_ptr_reg)
+                        full_next = 1'b1;
+                end
+
+            2'b11: begin
+                w_ptr_next = w_ptr_succ;
+                r_ptr_next = r_ptr_succ;
+            end
+        endcase
+    end
+
+    //Set Full and Empty
+    assign full = full_reg;
+    assign empty = empty_reg;
+    assign level = level_reg;
+
+endmodule

hdl/rtl/glitch_filter.v

@@ -0,0 +1,40 @@
+/*
+    A glitch filter
+*/
+module glitch_filter #(parameter N = 8, CLKDIV = 8'd1) (
+    input   wire    clk,
+    input   wire    rst_n,
+    input   wire    in,
+    input   wire    en,
+    output  reg     out
+);
+
+    reg [N-1:0] shifter;
+    wire        tick;
+
+    aucohl_ticker ticker (
+        .clk(clk),
+        .rst_n(rst_n),
+	.en(en),
+        .clk_div(CLKDIV),
+        .tick(tick)
+    );
+
+    always @(posedge clk, negedge rst_n)
+        if(!rst_n)
+            shifter <= 'b0;
+        else if(tick)
+            shifter <= {shifter[N-2:0], in};
+
+    wire all_ones   = & shifter;
+    wire all_zeros  = ~| shifter;
+
+    always @(posedge clk, negedge rst_n)
+        if(!rst_n)
+            out <= 1'b0;
+        else
+            if(all_ones) 
+                out <= 1'b1;
+            else if(all_zeros) 
+                out <= 1'b0;
+endmodule

hdl/rtl/sync.v

@@ -0,0 +1,17 @@
+/*
+    Brute-force Synchronizer
+*/
+module aucohl_sync #(parameter NUM_STAGES = 2) (
+    input wire clk,
+    input wire in,
+    output wire out
+);
+
+    reg [NUM_STAGES-1:0] sync;
+
+    always @(posedge clk)
+        sync <= {sync[NUM_STAGES-2:0], in};
+
+    assign out = sync[NUM_STAGES-1];
+
+endmodule