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Sample 64-bit functional units #119

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Hello,

The request contains 64-bit compatible sample functional units.

Latif Akçay

@pjaaskel
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Thanks for your contribution! Can you create a new hdb where these are included as FU entries so it is possible to use them in new 64b designs?

@LatifAkcayGithub
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Hello Pekka,

So sorry. That's my first time doing such a thing.
I think, I did it now :)
Beside the FU codes, I have added a HDB and IC_Decoder_Plugin that generates 64-bit compatible decoder.
Please check it.

Thanks

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Can you add a new systemtest that generates a 64b TTA with proge and simulates+verifies the resulting RTL? There are similar systemtests which use ghdl optionally under systemtests and systemtests_long. Also be sure to run the old tests and make sure all of them pass. Did you see this page? https://github.com/cpc/tce/wiki/Contributor-Info

@@ -0,0 +1,335 @@
-- Copyright (c) 2002-2009 Tampere University of Technology.
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Please check the copyright year, and the copyright also if you want to retain it. MIT license agreement is enough.

@@ -0,0 +1,260 @@
-- Copyright (c) 2002-2009 Tampere University of Technology.
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Here also.

@@ -0,0 +1,470 @@
-- Copyright (c) 2002-2009 Tampere University of Technology.
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...

-- Designer: Latif AKCAY
-- University: Bayburt University, Istanbul Technical University, TURKEY.

-- LSU64 Operations
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Perhaps this comment is redundant thanks to the nice list of contants below.

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-- Copyright (c) 2002-2009 Tampere University of Technology.
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...

data_out1_out <= "00000000000000000000000000000000" & data_out1_reg(31 downto 0); -- result has to be compatible with the currrent version of the operation!

end architecture rtl;

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pls remove the empty lines

@@ -30,6 +30,10 @@
* @author Vinogradov Viacheslav(added Verilog generating) 2012
* @note rating: red
*/

/*
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Please mind the 78 row size limit and also this type of comment belongs to git commit log, not in the source code. There you'd best describe what you did and preferably in more detail, why these changes were needed.

*fetchBlock);
toplevelBlock.netlist().connectPorts(
*ifetchCyclecountPort, *ttaCyclecountPort);
NetlistPort* ifetchLockcountPort = new NetlistPort(
"db_lockcnt", "32", 32, ProGe::BIT_VECTOR, HDB::OUT,
"db_lockcnt", "64", 64, ProGe::BIT_VECTOR, HDB::OUT,
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You force 64 here, does 32 RTL generation still work? Did you run tools/scripts/compiletest.sh to check the tests? Do you have 'ghdl' installed so it runs the RTL tests?

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2 participants