Skip to content

Issues: alexforencich/verilog-pcie

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

30 Open 21 Closed
30 Open 21 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

Link status has only Gen1*16
#58 opened Oct 7, 2024 by libero-x
7
Can you give the structure diagram of Verilog-pcie? Like Corundum
#57 opened Sep 28, 2024 by libero-x
why 'loading out-of-tree module taints kernel.' and 'example: module verification failed: signature and/or required key missing - tainting kernel'
#56 opened Aug 1, 2024 by Jaegerseki
1
Why is test data mismatching in example_driver
#54 opened Jun 6, 2024 by francoccc
3
dma + axi memory
#53 opened May 24, 2024 by juanma-rm
Implementation of the TL and DL functions of the PCIE protocol
#51 opened May 12, 2024 by KavinGarnet
1
why I run the test instance of tb , it report cannot import module dma_ram?
#50 opened May 2, 2024 by zhfff4869
2
python report the error about the path in dma_psdp_ram.py , why?
#49 opened May 2, 2024 by zhfff4869
1
make:No rule to make target
#48 opened Mar 21, 2024 by Jaegerseki
request for pcie axi slave verilog
#47 opened Mar 5, 2024 by vpsampath123
1
Segmented memory address bug caused by ram_mask_1_reg assertion in dma_if_pcie_rd.v
#46 opened Feb 3, 2024 by C0L
Which part is the digital part of Serdes Phy?
#45 opened Feb 2, 2024 by myqlee
2
I have two questions ,can someone help me
#43 opened Dec 24, 2023 by hdu-lpl
1
Using both DMA and separate AXI Slave as PCIe requester?
#40 opened Oct 3, 2023 by dbarrie
2
Implementation of PCIe “Non-Transparent Bridge" (NTB)
#39 opened Aug 29, 2023 by ohault
2
What name of the Top module name of all the verilogs in rtl folder?
#38 opened Aug 28, 2023 by asifikbal827
1
bug in dma_if_pcie_rd when max read request size is set to 4096 bytes
#35 opened Jul 7, 2023 by EricCSun
About pcie_us_if
#34 opened Jun 27, 2023 by GGbang2
1
How to test pcie_us_axi_dma on board?
#32 opened Nov 17, 2022 by hardikvala
FPGA versus FPGA_AXI Example Questions
#31 opened Aug 6, 2022 by softerhardware
10
Doc?
#30 opened May 15, 2022 by hughperkins
1
Support of CXL 2.0
#25 opened Jan 12, 2022 by ohault
dma_read_desc_status_valid not asserted when requesting memory read length > 8
#24 opened Jan 5, 2022 by filamoon
9
Support for Xilinx soft PCIe PHY?
#22 opened Jan 4, 2022 by Elgox2
1
Add Arria 10 device support enhancement New feature or request
#11 opened Feb 3, 2021 by alexforencich
ProTip! Adding no:label will show everything without a label.