Merge remote-tracking branch 'upstream/master' into difftest #31
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Update CSR_MCONTROL6_HIT to CSR_MCONTROL6_HIT0 Include CSR_TINFO_VERSION* macros
…d mcontrol6_t::hit Add mcontrol_common_t::set_hit()
Avoid using private headers, e.g., debug_defines.h, in triggers.h
…l6-hit0-hit1 Implement mcontrol6.hit
Based on Spec chapter 3.5 "An MRET or SRET instruction is used to return from a trap in M-mode or S-mode, respectively. When executing an xRET instruction, if xPP holds the value y, then ELP is set to the value of xPELP if yLPE is 1; otherwise, it is set to NO_LP_EXPECTED; xPELP is set to NO_LP_EXPECTED." The change follow the last statement after semicolon "xPELP is set to NO_LP_EXPECTED" Signed-off-by: Chih-Min Chao <[email protected]>
The spec says: "If vl=0, no operation is performed and the destination register is not updated." in Section 14. Vector Reduction Operations. The commit proposes setting the variable is_write to false when vl = 0, which means not logging the write.
zicflip: fix [ms]ret behavior
…reduction vector: Not logging write of reduction instructions when vl = 0
Accidentally removed in c9468f6. See riscv-software-src#1660.
…r/vxsat-write Require vector extension when attempting vxsat writes
When compiled as PIE, executable can be loaded at any memory address. Lately, OpenSBI switched to such behavior and spike was not able to load it anymore. This patch add an additional load_offset parameter for load_elf(). This load_offset value is passed as DRAM_BASE and used only for ET_DYN elfs. Signed-off-by: Clément Léger <[email protected]>
…er/et_dyn add support to load ET_DYN elf
ELP will be zero if Zicfilp is not enabled.
Serialize after setting ELP. That way, we can hoist the check outside of the main simulation loop.
…mplify-zicfilp Avoid checking ELP before every instruction fetch
Implement Debug spec Section 5.7.6. Trigger Control (tcontrol). This commit lets tcontrol be read-only 0 if number of triggers is 0.
triggers: implement tcontrol
- c.fsdsp need not be listed since cm.push etc. are listed - mop.r.28/mop.rr.7 don't have corresponding files in riscv/insns/ - the rest are just erroneous
We get better error checking if we list only the more specific instructions and omit the more general ones (mop.r.N/mop.rr.N).
It remains true that PTEs can only represent addresses >= 2^56, but there's no need to impose that constraint on untranslated accesses.
A previous commit removes the effectiveness of MPRV to MXR. (riscv-software-src#1784) However, the removal implies the MPRV affects point masking individually, and the MXR should consider the effective v bit.
pointer masking: Consider effective v bit instead of current v bit
ISA spec says "Setting MXR at HS-level overrides both VS-stage and G-stage execute-only permissions."
pointer masking: Always apply sstatus.MXR regardless of effective V
For mcontrol6, default to BEFORE timing.
…pport-larger-addresses Lift restriction on physical-address size
…r single-width integer multiply-add instructions
…r widening integer multiply-add instructions
…r single-width floating-point fused multiply-add instructions
…r widening floating-point fused multiply-add instructions
vector: disassemble: Let operand ordering be vd, [vrf]s1, vs2 to vector multiply-add instructions
* Revert "Lift restriction on physical-address size" This reverts commit 52f045d. * fix some merge compile errors
poemonsense
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Sep 6, 2024
lewislzh
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Dec 3, 2024
Merge remote-tracking branch 'upstream/master' into difftest
lewislzh
added a commit
that referenced
this pull request
Dec 3, 2024
Merge remote-tracking branch 'upstream/master' into difftest
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