Merge pull request #31 from OpenXiangShan/dbltrp

Merge remote-tracking branch 'upstream/master' into difftest

.github/workflows/debug-smoke.yml

@@ -47,7 +47,7 @@ jobs:
         run: |
           git clone --recurse-submodules https://github.com/riscv-software-src/riscv-tests.git
           cd riscv-tests
-          git checkout bd0a19c136927eaa3b7296a591a896c141affb6b
+          git checkout e06a435c1e545def71e833031356372f0828f165
 
       - name: Run Tests
         run: |

Makefile.in

@@ -385,6 +385,15 @@ install-hdrs : $(install_hdrs)
     $(INSTALL_HDR) $(src_dir)/$$file $(install_hdrs_dir)/`dirname $$file`; \
   done
 
+install-hdrs-list.h: $(install_hdrs)
+	rm -f $@.tmp
+	for file in $(subst $(src_dir)/,,$^); \
+	do \
+		$(MKINSTALLDIRS) $(install_hdrs_dir)/`dirname $$file`; \
+		echo "#include <$(src_dir)/$$file>" >> $@.tmp; \
+	done
+	mv $@.tmp $@
+
 install-libs : $(install_libs)
 	$(MKINSTALLDIRS) $(install_libs_dir)
 	for file in $^; \

README.md

@@ -13,8 +13,10 @@ Spike supports the following RISC-V ISA features:
   - RV32E and RV64E base ISAs, v1.9
   - Zifencei extension, v2.0
   - Zicsr extension, v2.0
+  - Zicntr extension, v2.0
   - M extension, v2.0
   - A extension, v2.1
+  - B extension, v1.0
   - F extension, v2.2
   - D extension, v2.2
   - Q extension, v2.2
@@ -37,11 +39,22 @@ Spike supports the following RISC-V ISA features:
   - Svnapot extension, v1.0
   - Svpbmt extension, v1.0
   - Svinval extension, v1.0
+  - Svadu extension, v1.0
   - Sdext extension, v1.0-STABLE
   - Sdtrig extension, v1.0-STABLE
   - Smepmp extension v1.0
   - Smstateen extension, v1.0
+  - Smdbltrp extension, v1.0
   - Sscofpmf v0.5.2
+  - Ssdbltrp extension, v1.0
+  - Ssqosid extension, v1.0
+  - Zaamo extension, v1.0
+  - Zalrsc extension, v1.0
+  - Zabha extension, v1.0
+  - Zacas extension, v1.0
+  - Zawrs extension, v1.0
+  - Zicfiss extension, v1.0
+  - Zicfilp extension, v1.0
   - Zca extension, v1.0
   - Zcb extension, v1.0
   - Zcf extension, v1.0
@@ -51,6 +64,19 @@ Spike supports the following RISC-V ISA features:
   - Zfbfmin extension, v0.6
   - Zvfbfmin extension, v0.6
   - Zvfbfwma extension, v0.6
+  - Zvbb extension, v1.0
+  - Zvbc extension, v1.0
+  - Zvkg extension, v1.0
+  - Zvkned extension, v1.0
+  - Zvknha, Zvknhb extension, v1.0
+  - Zvksed extension, v1.0
+  - Zvksh extension, v1.0
+  - Zvkt  extension, v1.0
+  - Zvkn, Zvknc, Zvkng extension, v1.0
+  - Zvks, Zvksc, Zvksg extension, v1.0 
+  - Zicond extension, v1.0
+  - Zilsd extension, v0.9.0
+  - Zcmlsd extension, v0.9.0
 
 Versioning and APIs
 -------------------
@@ -74,7 +100,7 @@ Build Steps
 We assume that the RISCV environment variable is set to the RISC-V tools
 install path.
 
-    $ apt-get install device-tree-compiler libboost-regex-dev
+    $ apt-get install device-tree-compiler libboost-regex-dev libboost-system-dev
     $ mkdir build
     $ cd build
     $ ../configure --prefix=$RISCV

ci-tests/build-spike

@@ -11,7 +11,7 @@ mkdir install
 CXXFLAGS="-Wnon-virtual-dtor" CFLAGS="-Werror -Wignored-qualifiers -Wunused-function -Wunused-parameter -Wunused-variable" $DIR/../configure --prefix=`pwd`/install
 make -j"$(nproc 2> /dev/null || sysctl -n hw.ncpu)"
 make check
-make install
+make install install-hdrs-list.h
 
 # check that help message prints without error
 install/bin/spike -h

ci-tests/test-spike

@@ -13,8 +13,11 @@ tar xf spike-ci.tar
 time ../install/bin/spike --isa=rv64gc pk hello | grep "Hello, world!  Pi is approximately 3.141588."
 
 # check that including sim.h in an external project works
-g++ -std=c++17 -I../install/include -L../install/lib $DIR/testlib.c -lriscv -o test-libriscv
-g++ -std=c++17 -I../install/include -L../install/lib $DIR/test-customext.cc -lriscv -o test-customext
+g++ -std=c++2a -I../install/include -L../install/lib $DIR/testlib.cc -lriscv -o test-libriscv
+g++ -std=c++2a -I../install/include -L../install/lib $DIR/test-customext.cc -lriscv -o test-customext
+
+# check that all installed headers are functional
+g++ -std=c++2a -I../install/include -L../install/lib $DIR/testlib.cc -lriscv -o /dev/null -include ../install-hdrs-list.h
 
 LD_LIBRARY_PATH=../install/lib ./test-libriscv pk hello| grep "Hello, world!  Pi is approximately 3.141588."
 LD_LIBRARY_PATH=../install/lib ./test-customext pk dummy-slliuw | grep "Executed successfully"

config.h.in

@@ -12,9 +12,6 @@
 /* Default value for --priv switch */
 #undef DEFAULT_PRIV
 
-/* Default value for --varch switch */
-#undef DEFAULT_VARCH
-
 /* Define if subproject MCPPBS_SPROJ_NORM is enabled */
 #undef DISASM_ENABLED
 

configure

@@ -739,7 +739,6 @@ with_boost_asio
 with_boost_regex
 with_isa
 with_priv
-with_varch
 with_target
 enable_dual_endian
 '
@@ -1407,8 +1406,6 @@ Optional Packages:
   --with-isa=RV64IMAFDC_zicntr_zihpm
                           Sets the default RISC-V ISA
   --with-priv=MSU         Sets the default RISC-V privilege modes supported
-  --with-varch=vlen:128,elen:64
-                          Sets the default vector config
   --with-target=riscv64-unknown-elf
                           Sets the default target config
 
@@ -6593,20 +6590,6 @@ fi
 
 
 
-# Check whether --with-varch was given.
-if test ${with_varch+y}
-then :
-  withval=$with_varch;
-printf "%s\n" "#define DEFAULT_VARCH \"$withval\"" >>confdefs.h
-
-else $as_nop
-
-printf "%s\n" "#define DEFAULT_VARCH \"vlen:128,elen:64\"" >>confdefs.h
-
-fi
-
-
-
 # Check whether --with-target was given.
 if test ${with_target+y}
 then :

difftest/difftest.cc

@@ -447,7 +447,6 @@ const cfg_t *DifftestRef::create_cfg() {
   cfg->bootargs = nullptr;
   cfg->isa = CONFIG_DIFF_ISA_STRING;
   cfg->priv = DEFAULT_PRIV;
-  cfg->varch = DEFAULT_VARCH;
   cfg->misaligned = false;
     // const endianness_t default_endianness,
   cfg->endianness = endianness_little;