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arch-riscv: cherry-pick zcb support from upstream #252

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merged 2 commits into from
Jan 2, 2025
Merged

arch-riscv: cherry-pick zcb support from upstream #252

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c600767
arch-riscv: Implement Zcb instructions
rogerchang23424 Jul 5, 2023
97c8102
arch-riscv: remove rv32 related code
eastonman Dec 29, 2024
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2 changes: 2 additions & 0 deletions src/arch/riscv/isa/bitfields.isa
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Original file line number Diff line number Diff line change
Expand Up @@ -95,7 +95,9 @@ def bitfield RL <25>;

// Compressed
def bitfield COPCODE <15:13>;
def bitfield CFUNCT6LOW3 <12:10>;
def bitfield CFUNCT1 <12>;
def bitfield CFUNCT1BIT6 <6>;
def bitfield CFUNCT2HIGH <11:10>;
def bitfield CFUNCT2LOW <6:5>;
def bitfield RC1 <11:7>;
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66 changes: 66 additions & 0 deletions src/arch/riscv/isa/decoder.isa
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Expand Up @@ -81,6 +81,49 @@ decode QUADRANT default Unknown::unknown() {
EA = Rp1 + offset;
}});
}
0x4: decode CFUNCT6LOW3 {
format CompressedLoad {
0x0: c_lbu({{
offset = (CIMM2<0:0> << 1) | CIMM2<1:1>;
}}, {{
Rp2 = Mem_ub;
}}, {{
EA = (Rp1 + offset);
}});
0x1: decode CFUNCT1BIT6 {
0x0: c_lhu({{
offset = CIMM2<0:0> << 1;
}}, {{
Rp2 = Mem_uh;
}}, {{
EA = (Rp1 + offset);
}});
0x1: c_lh({{
offset = CIMM2<0:0> << 1;
}}, {{
Rp2_sd = Mem_sh;
}}, {{
EA = (Rp1 + offset);
}});
}
}
format CompressedStore {
0x2: c_sb({{
offset = (CIMM2<0:0> << 1) | CIMM2<1:1>;
}}, {{
Mem_ub = Rp2_ub;
}}, ea_code={{
EA = (Rp1 + offset);
}});
0x3: c_sh({{
offset = (CIMM2<0:0> << 1);
}}, {{
Mem_uh = Rp2_uh;
}}, ea_code={{
EA = (Rp1 + offset);
}});
}
}
format CompressedStore {
0x5: c_fsd({{
offset = CIMM3 << 3 | CIMM2 << 6;
Expand Down Expand Up @@ -235,6 +278,29 @@ decode QUADRANT default Unknown::unknown() {
0x1: c_addw({{
Rp1_sd = (int32_t)Rp1_sd + Rp2_sw;
}});
0x2: c_mul({{
Rp1_sd = (Rp1_sd * Rp2_sd);
}}, IntMultOp);
0x3: decode RP2 {
0x0: c_zext_b({{
Rp1 = Rp1 & 0xFFULL;
}});
0x1: c_sext_b({{
Rp1 = sext<8>(Rp1 & 0xFFULL);
}});
0x2: c_zext_h({{
Rp1 = Rp1 & 0xFFFFULL;
}});
0x3: c_sext_h({{
Rp1 = sext<16>(Rp1 & 0xFFFFULL);
}});
0x4: c_zext_w({{
Rp1 = bits(Rp1, 31, 0);
}});
0x5: c_not({{
Rp1 = ~Rp1;
}});
}
}
}
}
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5 changes: 3 additions & 2 deletions src/arch/riscv/isa/formats/compressed.isa
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Expand Up @@ -152,8 +152,9 @@ def template CBasicExecute {{
std::vector<RegId> indices = {%(regs)s};
std::stringstream ss;
ss << mnemonic << ' ';
ss << registerName(indices[0]) << ", ";
ss << registerName(indices[1]);
ss << registerName(indices[0]);
if (_numSrcRegs >= 2)
ss << ", " << registerName(indices[1]);
return ss.str();
}
}};
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