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Fix some bugs to run splash3 benchmarks #165

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merged 9 commits into from
Aug 30, 2024
Merged

Fix some bugs to run splash3 benchmarks #165

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56ac322
arch-riscv: Add dummy mtval2 and mtinst
notlqr Aug 4, 2024
2a66c3d
misc: use clint instead of lint
notlqr Aug 11, 2024
0354315
cpu-o3: Add store buffer entry timeout
notlqr Aug 13, 2024
7aaf067
arch-riscv: let fcvt/fmv/fsgnj update mstatus.fs if dst is fpr
notlqr Aug 15, 2024
f499f1f
mem-ruby: Fix atomic insts not marking cache line busy
notlqr Aug 15, 2024
1f08a12
cpu: better difftest logging
notlqr Aug 22, 2024
20a6f0a
cpu: Fix interrupt handling
notlqr Aug 26, 2024
c501004
arch-riscv: Fix bugs of sfence.vma
jueshiwenli Aug 27, 2024
afab0f9
cpu-o3: Fix sbuffer stuck when split store's insertion fails
notlqr Aug 27, 2024
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3 changes: 1 addition & 2 deletions configs/common/FSConfig.py
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Original file line number Diff line number Diff line change
Expand Up @@ -678,11 +678,10 @@ def makeBareMetalXiangshanSystem(mem_mode, mdesc=None, cmdline=None, np=1, ruby=
self.uartlite = UartLite()
self.uartlite.pio = self.iobus.mem_side_ports

self.lint = Lint()
self.lint = Clint()
self.lint.pio = self.iobus.mem_side_ports
self.lint.pio_addr = 0x38000000
self.lint.num_threads = np
self.lint.int_enable = 1

self.mmcs = NemuMMC()
self.mmcs.pio = self.iobus.mem_side_ports
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2 changes: 2 additions & 0 deletions src/arch/riscv/gdb-xml/riscv-64bit-csr.xml
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Expand Up @@ -229,6 +229,8 @@
<reg name="mhpmevent29" bitsize="64"/>
<reg name="mhpmevent30" bitsize="64"/>
<reg name="mhpmevent31" bitsize="64"/>
<reg name="mtinst" bitsize="64"/>
<reg name="mtval2" bitsize="64"/>
<reg name="tselect" bitsize="64"/>
<reg name="tdata1" bitsize="64"/>
<reg name="tdata2" bitsize="64"/>
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4 changes: 4 additions & 0 deletions src/arch/riscv/isa.cc
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Expand Up @@ -138,6 +138,10 @@ namespace RiscvISA
[MISCREG_HPMEVENT29] = "HPMEVENT29",
[MISCREG_HPMEVENT30] = "HPMEVENT30",
[MISCREG_HPMEVENT31] = "HPMEVENT31",

[MISCREG_MTINST] = "MTINST",
[MISCREG_MTVAL2] = "MTVAL2",

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[MISCREG_TSELECT] = "TSELECT",
[MISCREG_TDATA1] = "TDATA1",
[MISCREG_TDATA2] = "TDATA2",
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36 changes: 36 additions & 0 deletions src/arch/riscv/isa/decoder.isa
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Expand Up @@ -1660,29 +1660,41 @@ decode QUADRANT default Unknown::unknown() {
auto sign = bits(unboxF32(Fs2_bits), 31);
Fd_bits = boxF32(insertBits(unboxF32(Fs1_bits), 31,
sign));
status.fs = 3;
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xc->setMiscReg(MISCREG_STATUS,status);
}}, FloatMiscOp);
0x1: fsgnjn_s({{
auto sign = ~bits(unboxF32(Fs2_bits), 31);
Fd_bits = boxF32(insertBits(unboxF32(Fs1_bits), 31,
sign));
status.fs = 3;
xc->setMiscReg(MISCREG_STATUS,status);
}}, FloatMiscOp);
0x2: fsgnjx_s({{
auto sign = bits(
unboxF32(Fs1_bits) ^ unboxF32(Fs2_bits), 31);
Fd_bits = boxF32(insertBits(unboxF32(Fs1_bits), 31,
sign));
status.fs = 3;
xc->setMiscReg(MISCREG_STATUS,status);
}}, FloatMiscOp);
}
0x11: decode ROUND_MODE {
0x0: fsgnj_d({{
Fd_bits = insertBits(Fs2_bits, 62, 0, Fs1_bits);
status.fs = 3;
xc->setMiscReg(MISCREG_STATUS,status);
}}, FloatMiscOp);
0x1: fsgnjn_d({{
Fd_bits = insertBits(~Fs2_bits, 62, 0, Fs1_bits);
status.fs = 3;
xc->setMiscReg(MISCREG_STATUS,status);
}}, FloatMiscOp);
0x2: fsgnjx_d({{
Fd_bits = insertBits(
Fs1_bits ^ Fs2_bits, 62, 0, Fs1_bits);
status.fs = 3;
xc->setMiscReg(MISCREG_STATUS,status);
}}, FloatMiscOp);
}
0x12: decode ROUND_MODE {
Expand Down Expand Up @@ -1800,6 +1812,8 @@ decode QUADRANT default Unknown::unknown() {
freg_t fd;
fd = freg(f64_to_f32(f64(freg(Fs1_bits))));
Fd_bits = fd.v;
status.fs = 3;
xc->setMiscReg(MISCREG_STATUS,status);
}}, FloatCvtOp);
0x2: fcvt_s_h({{
RM_REQUIRED;
Expand All @@ -1814,6 +1828,8 @@ decode QUADRANT default Unknown::unknown() {
freg_t fd;
fd = freg(f32_to_f64(f32(freg(Fs1_bits))));
Fd_bits = fd.v;
status.fs = 3;
xc->setMiscReg(MISCREG_STATUS,status);
}}, FloatCvtOp);
0x2: fcvt_d_h({{
RM_REQUIRED;
Expand Down Expand Up @@ -1965,42 +1981,58 @@ decode QUADRANT default Unknown::unknown() {
freg_t fd;
fd = freg(i32_to_f32((int32_t)Rs1_sw));
Fd_bits = fd.v;
status.fs = 3;
xc->setMiscReg(MISCREG_STATUS,status);
}}, FloatCvtOp);
0x1: fcvt_s_wu({{
RM_REQUIRED;
freg_t fd;
fd = freg(ui32_to_f32((uint32_t)Rs1_uw));
Fd_bits = fd.v;
status.fs = 3;
xc->setMiscReg(MISCREG_STATUS,status);
}}, FloatCvtOp);
0x2: fcvt_s_l({{
RM_REQUIRED;
freg_t fd;
fd = freg(i64_to_f32(Rs1_ud));
Fd_bits = fd.v;
status.fs = 3;
xc->setMiscReg(MISCREG_STATUS,status);
}}, FloatCvtOp);
0x3: fcvt_s_lu({{
RM_REQUIRED;
freg_t fd;
fd = freg(ui64_to_f32(Rs1));
Fd_bits = fd.v;
status.fs = 3;
xc->setMiscReg(MISCREG_STATUS,status);
}}, FloatCvtOp);
}
0x69: decode CONV_SGN {
0x0: fcvt_d_w({{
RM_REQUIRED;
Fd = (double)Rs1_sw;
status.fs = 3;
xc->setMiscReg(MISCREG_STATUS,status);
}}, FloatCvtOp);
0x1: fcvt_d_wu({{
RM_REQUIRED;
Fd = (double)Rs1_uw;
status.fs = 3;
xc->setMiscReg(MISCREG_STATUS,status);
}}, FloatCvtOp);
0x2: fcvt_d_l({{
RM_REQUIRED;
Fd = (double)Rs1_sd;
status.fs = 3;
xc->setMiscReg(MISCREG_STATUS,status);
}}, FloatCvtOp);
0x3: fcvt_d_lu({{
RM_REQUIRED;
Fd = (double)Rs1;
status.fs = 3;
xc->setMiscReg(MISCREG_STATUS,status);
}}, FloatCvtOp);
}
0x6a: decode CONV_SGN {
Expand Down Expand Up @@ -2063,11 +2095,15 @@ decode QUADRANT default Unknown::unknown() {
freg_t fd;
fd = freg(f32(Rs1_uw));
Fd_bits = fd.v;
status.fs = 3;
xc->setMiscReg(MISCREG_STATUS,status);
}}, FloatCvtOp);
0x79: fmv_d_x({{
freg_t fd;
fd = freg(f64(Rs1));
Fd_bits = fd.v;
status.fs = 3;
xc->setMiscReg(MISCREG_STATUS,status);
}}, FloatCvtOp);
0x7a: fmv_h_x({{
freg_t fd;
Expand Down
10 changes: 10 additions & 0 deletions src/arch/riscv/regs/misc.hh
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Expand Up @@ -132,6 +132,10 @@ enum MiscRegIndex
MISCREG_HPMEVENT29,
MISCREG_HPMEVENT30,
MISCREG_HPMEVENT31,

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MISCREG_MTINST,
MISCREG_MTVAL2,

MISCREG_TSELECT,
MISCREG_TDATA1,
MISCREG_TDATA2,
Expand Down Expand Up @@ -366,6 +370,9 @@ enum CSRIndex
CSR_MHPMEVENT30 = 0x33E,
CSR_MHPMEVENT31 = 0x33F,

CSR_MTINST = 0x34A,
CSR_MTVAL2 = 0x34B,

CSR_TSELECT = 0x7A0,
CSR_TDATA1 = 0x7A1,
CSR_TDATA2 = 0x7A2,
Expand Down Expand Up @@ -544,6 +551,9 @@ const std::map<int, CSRMetadata> CSRData = {
{CSR_MHPMEVENT30, {"mhpmevent30", MISCREG_HPMEVENT30}},
{CSR_MHPMEVENT31, {"mhpmevent31", MISCREG_HPMEVENT31}},

{CSR_MTINST, {"mtisnt", MISCREG_MTINST}},
{CSR_MTVAL2, {"mtval2", MISCREG_MTVAL2}},

{CSR_TSELECT, {"tselect", MISCREG_TSELECT}},
{CSR_TDATA1, {"tdata1", MISCREG_TDATA1}},
{CSR_TDATA2, {"tdata2", MISCREG_TDATA2}},
Expand Down
13 changes: 6 additions & 7 deletions src/arch/riscv/tlb.cc
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Expand Up @@ -781,7 +781,6 @@ TLB::demapPage(Addr vpn, uint64_t asid)
DPRINTF(TLB, "flush(vpn=%#x, asid=%#x)\n", vpn, asid);
DPRINTF(TLB, "l1tlb flush(vpn=%#x, asid=%#x)\n", vpn, asid);
if (vpn != 0 && asid != 0) {
assert(0);

TlbEntry *newEntry = lookup(vpn, asid, BaseMMU::Read, true, false);
if (newEntry)
Expand All @@ -807,22 +806,22 @@ TLB::demapPageL2(Addr vpn, uint64_t asid)
{
asid &= 0xFFFF;
std::vector<Addr> vpn_vec;
std::vector<std::vector<TlbEntry>> tlb_lists;
std::vector<TlbEntry *> tlb_lists;
vpn_vec.push_back(0);
Addr vpnl2l1 = (vpn >> (PageShift + 2 * LEVEL_BITS + L2TLB_BLK_OFFSET))
<< (PageShift + 2 * LEVEL_BITS + L2TLB_BLK_OFFSET);
vpn_vec.push_back(vpnl2l1);
tlb_lists.push_back(tlbL2L1);
tlb_lists.push_back(tlbL2L1.data());
Addr vpnl2l2 = (vpn >> (PageShift + LEVEL_BITS + L2TLB_BLK_OFFSET)) << (PageShift + LEVEL_BITS + L2TLB_BLK_OFFSET);
vpn_vec.push_back(vpnl2l2);
tlb_lists.push_back(tlbL2L2);
tlb_lists.push_back(tlbL2L2.data());
Addr vpnl2l3 = (vpn >> (PageShift + L2TLB_BLK_OFFSET)) << (PageShift + L2TLB_BLK_OFFSET);
vpn_vec.push_back(vpnl2l3);
tlb_lists.push_back(tlbL2L3);
tlb_lists.push_back(tlbL2L3.data());
Addr vpnl2sp1 = (vpn >> (PageShift + 2 * LEVEL_BITS + L2TLB_BLK_OFFSET))
<< (PageShift + 2 * LEVEL_BITS + L2TLB_BLK_OFFSET);
vpn_vec.push_back(vpnl2sp1);
tlb_lists.push_back(tlbL2Sp);
tlb_lists.push_back(tlbL2Sp.data());
Addr vpnl2sp2 = (vpn >> (PageShift + LEVEL_BITS + L2TLB_BLK_OFFSET))
<< (PageShift + LEVEL_BITS + L2TLB_BLK_OFFSET);
vpn_vec.push_back(vpnl2sp2);
Expand All @@ -847,7 +846,7 @@ TLB::demapPageL2(Addr vpn, uint64_t asid)
if (l2_newEntry[i]) {
TlbEntry *m_newEntry = lookupL2TLB(vpn_vec[i], asid, BaseMMU::Read, true, i, false);
assert(m_newEntry != nullptr);
l2TLBRemove(m_newEntry - tlb_lists[tlb_i].data(), i);
l2TLBRemove(m_newEntry - tlb_lists[tlb_i], i);
}
}
} else {
Expand Down
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