Python Automation

This release introduces Python scripts to automate the creation of a build directory with all the necessary files and build makefiles for running emulation, RTL simulation, and FPGA. There are also significant advances in the automatic creation of Control and Status Register (CSR) files, comprising both the hardware and bare-metal software and in generating standard interfaces such as AXI4 and AMBA. The UART and LIB submodules have been integrated into IOb-SoC, which reduces the use of git submodules and associated problems.

What's Changed

• Uartdev merged to verilator and the relevant pushes applied to finish up the rest of the verilator testbench by @slahiruk in #107
• Verilator updates to wrapper by @slahiruk in #108
• Verilator changes to include wrapper by @slahiruk in #110
• Verilator new changes by @slahiruk in #111
• Verilator, add cpu_tasks.v after merging master by @slahiruk in #112
• Verilator by @PedroAntunes178 in #195
• Verilator by @PedroAntunes178 in #197
• Master merge by @PedroAntunes178 in #234
• Verilator by @PedroAntunes178 in #235
• Verilator by @PedroAntunes178 in #236
• Verilator by @PedroAntunes178 in #269
• Verilator by @PedroAntunes178 in #274
• update CACHE and MEM submodules; update sources according new version of the submodules by @JDLopes in #293
• fix(test): Update test.expected files by @P-Miranda in #294
• update(MEM): Update MEM with python3 by @P-Miranda in #295
• Update submodules, fix simulation by @P-Miranda in #296
• fix(doc): Update documentation path by @P-Miranda in #297
• Fix simulation, update test.expected, update UART submodule by @P-Miranda in #299
• fix(test): Better cleanup of extra files, Update expected logs for test by @P-Miranda in #301
• Improve test.expected logs, Update docs and README by @P-Miranda in #303
• fix USER variable when execute queue-out-remote in FPGA Makefiles by @JDLopes in #304
• Update submodules and documentation by @P-Miranda in #305
• update(doc): new steps to add timer by @P-Miranda in #306
• copy VCD file in case of Ctrl+C is pressed by @JDLopes in #309
• add(submodules): Single level submodule dependency by @P-Miranda in #310
• fix(AXI): Fix path to AXI submodule; Update UART by @P-Miranda in #311
• Verilator by @PedroAntunes178 in #312
• Verilator by @PedroAntunes178 in #313
• Verilator by @PedroAntunes178 in #314
• switched to devel for future work from now on by @microSharjeel in #318
• Verilator by @PedroAntunes178 in #319
• Verilator by @PedroAntunes178 in #320
• changes in targets ....combined and removed by @microSharjeel in #322
• changes to add sp ram in sram.v after merge with devel by @microSharjeel in #323
• changes for addition of USE_SPRAM by @microSharjeel in #324
• Verilator by @PedroAntunes178 in #328
• Verilator devel by @PedroAntunes178 in #329
• fix .sdc file generation for ASIC; rename ASIC report files extention; update all submodules; update sources by @JDLopes in #332
• update system.v and system_tb.v targets; update system_core_tb.v file; update CACHE submodule by @JDLopes in #333
• update UART submodule by @JDLopes in #335
• Verilator by @PedroAntunes178 in #334
• Updated with iob-soc devel branch; Initial version of modelsim working by @P-Miranda in #336
• update LIB submodule; fix documents generation; update PDFs and test.expected files by @JDLopes in #337
• INIT_MEM=0 should be set manually by @PedroAntunes178 in #338
• Verilator by @PedroAntunes178 in #341
• merge with iob-soc/verilator; remove coco_tb by @JDLopes in #342
• minor improvements; update AXI submodule by @JDLopes in #343
• fix .gitignore file; add verilator to simulation tests; cleanup simulation.mk file; remove debug code lines from testbenches; fix console; add test.expected file for verilator; add ifdef VCD to verilator testbench; update test.expected files; centralize console call; update LIB submodule; update synscript.tcl according new LIB version by @JDLopes in #344
• fix remote simulation by @JDLopes in #345
• fix console when receive file name via FPGA; remove dummy test target; update test.expected files for FPGAs; cleanup clean targets for FPGAs by @JDLopes in #346
• Devel by @PedroAntunes178 in #347
• update test.expected for Verilator by @JDLopes in #354
• update test.expected file for product brief by @JDLopes in #356
• update UART submodule by @JDLopes in #357
• fix kill console both on simulation and FPGA run by @JDLopes in #359
• Fixed bug that caused the verilator testbench to not pass the second test by @PedroAntunes178 in #360
• fix INIT_MEM for simulation when it's not set on the command; fix console kill process by @JDLopes in #361
• Removed fseek and truncate from console and testbench. by @PedroAntunes178 in #363
• update AXI submodule; update sources according new AXI version by @JDLopes in #364
• update AXI submodule by @JDLopes in #365
• change default serial port to connect to FPGAs by @JDLopes in #366
• kill console in case of a trap by @JDLopes in #368
• fix(console): usage error | fix(sw): Warning for possible misaligned accesses by @P-Miranda in #370
• fix console to print non-ascii characteres like copyright by @JDLopes in #371
• fix kill console when FPGA run is interrupted; move define in CycloneV Makefile by @JDLopes in #373
• Fix ser.read(file_size) would not receive full s_fw.bin; by @PedroAntunes178 in #374
• fix reset in testbench; remove unused signal in top_system.v file for AES-KU040-DB-G FPGA; update MEM submodule by @JDLopes in #377
• feat: changes to support ethernet core integration by @P-Miranda in #378
• fix(fpga): special handling of TEST_LOG by @P-Miranda in #379
• Call Console from PC-emul Makefile. by @PedroAntunes178 in #380
• Fix fpga-test, update docs by @P-Miranda in #382
• remove dummy target from quartus.mk by @JDLopes in #383
• Improve drivers, Update LIB UART by @P-Miranda in #385
• Simplify system_core_tb.v; Now Icarus also uses system_top.v by @PedroAntunes178 in #386
• Fix bug in firmware.S by @arturum1 in #387
• fix baudrate setting for pc-emul, simulation, FPGA and ASIC; set serial port timeout to None in console; change default baudrate to 115200 in config.mk by @JDLopes in #388
• Fix tests by @JDLopes in #390
• fix tests by @JDLopes in #391
• Minor improvements by @JDLopes in #393
• Minor improvements by @jjts in #394
• feat(doc): Review README and presentation by @P-Miranda in #395
• feat(doc): update test.expected by @P-Miranda in #396
• fix variable name by @JDLopes in #397
• feat(LIB): update LIB, UART submodules by @P-Miranda in #398
• Add multi-instance capability; Remove 'pio.vh' and 'inst.vh' file dependency. by @arturum1 in #400
• fix xcelium Makefile by @JDLopes in #401
• rename module name from TOP to system_tb by @JDLopes in #403
• run sed command only when VCD=1 by @JDLopes in #404
• remove ASIC folders and references by @JDLopes in #406
• remove MEM and AXI submodules; update sources by @JDLopes in #407
• try to fix console errors for FPGA by @JDLopes in #408
• Add configurable verilog parameters to peripherals; Use parameters instead of macros to allow definition at instantiation; Fix bugs. by @arturum1 in #409
• Update LIB and UART with latest mkregs by @P-Miranda in #410
• feat(mkregs): update LIB, UART, cpu tasks by @P-Miranda in #411
• feat(actions): update default shell by @P-Miranda in #412
• update test.expected files; update README.md by @JDLopes in #413
• feat(actions): Add workflow concurrency by @P-Miranda in #414
• force INIT_MEM=0 when RUN_EXTMEM=1 for FPGAs by @JDLopes in #416
• Merge branch 'master'; Dont add parameter list if there are no parameters. by @arturum1 in #415
• feat(actions): stop job if previous was cancelled by @P-Miranda in #417
• feat(diff): Print difference for test.expected by @P-Miranda in #419
• Merge branch 'master' into system by @arturum1 in #420
• feat(sw): firmware creates transfered file by @P-Miranda in #421
• fix(tests): Fix pc-emul, icarus and fpga tests by @P-Miranda in #422
• Change PERIPHERALS parameters from (...) to [...] . by @arturum1 in #423
• Enable support for multiple clk's in the verilator test-bench; Update gitignore file; by @PedroAntunes178 in #418
• Update LIB submodule; Add feature to console; Use fixed Periphral and Boot bit; Add split between internal and external data bus in system_core; by @PedroAntunes178 in #424
• Update LIB submodule; Move console from iob-soc to iob-lib; Use console in iob-lib; by @PedroAntunes178 in #425
• Merge branch 'master' into system by @arturum1 in #427
• Fix bug parsing peripherals list. by @arturum1 in #428
• Fix: Verilator testbench compiles taking into consideration the macros defined by the IOb-SoC makefiles; Verilator .cpp file is not to be ignored by git; by @PedroAntunes178 in #426
• Simplify reset sequence; Fix not showing reset trace; by @PedroAntunes178 in #432
• fix signal name in Verilator testbench by @JDLopes in #435
• Ddr3 by @jjts in #434
• Build-dir by @JDLopes in #436
• Update python scripts to replace Verilog parameters in peripheral IO signals by their value. by @arturum1 in #437
• Update LIB, setup, pc-emul, embedded firmware by @P-Miranda in #442
• fix(CACHE): update CACHE commit by @P-Miranda in #443
• Merge system branch by @P-Miranda in #445
• Simulation working without DDR by @P-Miranda in #446
• fix(setup): generate version files by @P-Miranda in #448
• Update LIB; Update python scripts arguments; Update scripts directory from LIB. by @arturum1 in #449
• Update LIB; Update python scripts args; Remove GET_DIRS. by @arturum1 in #450
• feat(pc-emul): initial working pc-emul version by @P-Miranda in #458
• Fix: testbenchs; run in Cyclone V if it is not default board; missing iob_reg if iob-UART was not used; documentation expected results; by @PedroAntunes178 in #467
• increase simulation BAUD to speedup simulation time; do not remove commands.txt file on clean by @JDLopes in #468
• BASYS3 working by @JDLopes in #473
• Update LIB submodule to master HEAD; by @PedroAntunes178 in #475
• allow iob-soc being used for any BASYS3 FPGA board by @JDLopes in #476
• feat(build-lib): build dir generates successfully by @arturum1 in #478
• feat(build-lib): fix issues by @arturum1 in #479
• feat(software): fix software setup and build process by @arturum1 in #480
• Update IOb interface, Update submodules that update python scripts; by @PedroAntunes178 in #481
• Update LIB submodule; by @PedroAntunes178 in #482
• Update build-lib with recent master fixes; by @PedroAntunes178 in #483
• feat(iob_tasks): replace cpu_tasks by iob_tasks by @arturum1 in #484
• Compile bootloader correctly; Change signals name in acordance to new interface; by @PedroAntunes178 in #485
• feat(doc,sw): ug.tex builds successfully; include sources instead of copy; Update LIB by @arturum1 in #486
• [Int_mem] Fix ready signal; by @PedroAntunes178 in #487
• Update submodules, pass en_i to peripherals; by @PedroAntunes178 in #488
• IOb-SoC runs simulation with INIT_MEM=1 and RUN_EXTMEM=0; by @PedroAntunes178 in #489
• feat(verilator): fix verilator testbench; update ci.yml by @arturum1 in #490
• feat(ci.yml): fix ci.yml syntax by @arturum1 in #491
• Add meta variable; Use common defines in Sw and Hw; by @PedroAntunes178 in #492
• feat(setup.py,ci.yml): use nix-shell in ci.yml; update iob_soc_setup.py by @arturum1 in #493
• Setup: update python setup in LIB submodule; by @PedroAntunes178 in #496
• Setup: Deprecate sw_setup; Progress in FPGA setup; by @PedroAntunes178 in #497
• Simulation: progress in running simulation with RUN_EXTMEM=1; by @PedroAntunes178 in #498
• IOb interface: progress; (Cache not working) by @PedroAntunes178 in #499
• feat(python-setup): Update makefile segments and Verilog sources by @arturum1 in #500
• Update LIB submodule by @roby2014 in #502
• Fix firmware name; Add tests for INIT_MEM and RUN_EXTMEM. by @arturum1 in #503
• fpga-setup: Progress in building and running iob-soc in the FPGA; by @PedroAntunes178 in #504
• Add setup arguments; FPGA board configuration at build-time; Remove 'meta' dictionary. by @arturum1 in #513
• Adapt bootloader to console; add custom TCL script for Vivado; Fix FPGA_GRABBED and renamed it to BOARD_GRABBED; by @PedroAntunes178 in #514
• Update fpga test.expected; Update ci.yml to check documents; by @arturum1 in #515
• Fix IOB_SOC_RUN_EXTMEM macro name by @arturum1 in #516
• FPGA wrappers update by @arturum1 in #517
• vivado/AES-KU040-DB-G: enabled execution of all iob-soc modes on this FPGA board. by @PedroAntunes178 in #518
• Update Verilog module names and ports. by @arturum1 in #520
• Update build_configuration and its macros; Update module parameters. by @arturum1 in #523
• Minor changes by @arturum1 in #524
• feat(int_mem): Add missing include by @arturum1 in #525
• Update defines to use boolean values by @arturum1 in #526
• Add default.nix; Update README; Resolve issues. by @arturum1 in #530
• Update README by @arturum1 in #531
• Update Verilog and configuration according to new LIB. by @arturum1 in #532
• Update LIB by @arturum1 in #533
• Update LIB; Remove build_configuration.* includes. by @arturum1 in #534
• Update iob_reset_sync ports by @arturum1 in #535
• Add IOb-SoC specific python scripts taken from LIB; Allow IOb-SoC to be used as a submodule. by @arturum1 in #536
• Rename iob_soc_top.vt to iob_soc_sim_wrapper.vt by @arturum1 in #538
• Update test process. by @arturum1 in #540
• Update ci.yml, sram.v, and submodules. by @arturum1 in #544
• Update fpga_build.mk and fpga_setup.py; Update software scritps and structure. by @arturum1 in #545
• Update LIB and CONSOLE_CMD; Fix small bugs. by @arturum1 in #546
• Remove unneeded file; Update LIB. by @arturum1 in #548
• feat(format): format python, update LIB by @P-Miranda in #550
• Add peripheral port map functionality. by @arturum1 in #551
• feat(format): update LIB. Add clang format by @P-Miranda in #554
• *: clean IOb-SoC with verible linter. by @PedroAntunes178 in #556
• Update python-setup process; Add portmap for internal system interfaces. by @arturum1 in #555
• Add doc_only attribute to ios by @arturum1 in #558
• ghactions: fpga board make does not run inside nix by @PedroAntunes178 in #559
• *: deprecate the use of .vt, use .vs instead of PRAGMAS. by @PedroAntunes178 in #560
• *: rename similar .vs used in iob_soc.v and iob_soc_sim_wrapper.v by @PedroAntunes178 in #561
• Object oriented setup process; Merge iob-soc-tester. by @arturum1 in #557
• iob_soc_tb.v: fix formatting of macro call failed: paren_group not found. by @PedroAntunes178 in #563
• Shared external memory by @arturum1 in #564
• *: Simplificcation of the V, E, B and P bits. by @PedroAntunes178 in #565
• submodules/*: Update LIB submodule. by @PedroAntunes178 in #566
• ext_mem.v: update CACHE submodule. by @PedroAntunes178 in #567
• Fix trap signal of peripherals; Update iob_soc_firmware.S. by @arturum1 in #568
• submodule/*: Update LIB and PicoRV. by @PedroAntunes178 in #569
• Python setup by @AndreMerendeira in #570
• [CACHE] updated submodule by @AndreMerendeira in #572
• Update python class methods according to new LIB by @arturum1 in #571
• update(LIB): latest python-setup branch by @P-Miranda in #573
• submodules/*: update. by @PedroAntunes178 in #575
• *: added `include "iob_utils.vh" where necessary. by @PedroAntunes178 in #576
• Update scripts to use iob_module instances instead of the old iob_verilog_instance class. by @arturum1 in #574
• sw_build.mk: fix GET_MACRO. by @PedroAntunes178 in #578
• int_mem.v: init SRAM only if not using EXTMEM. by @PedroAntunes178 in #579
• Add new if_gen interfaces with reserved signals to portmap scripts. by @arturum1 in #580
• Suffix on UART signals and update LIB submodule by @Edw590 in #582
• Add _i/_o suffix to iob-soc, picorv32 and cache I/O ports by @Edw590 in #583
• Add printf dependency. by @arturum1 in #584
• submodules/LIB: update. by @PedroAntunes178 in #591
• [LIB] updated submodule by @AndreMerendeira in #598
• Add memory address offset param; Fix portmap signals; Fix cache driver issues. by @arturum1 in #594
• update(LIB): update LIB python-setup branch by @P-Miranda in #600
• update(LIB, UART): with latest python-setup by @P-Miranda in #601
• Move interconnect from iob_soc_utils.py to iob_soc.py by @arturum1 in #604
• update(LIB, UART, CACHE): submodules by @P-Miranda in #607

New Contributors

• @jjts made their first contribution in #394

Full Changelog: V0.6...V0.70