Bronze

This is the last release befor merging with branch if_gen2.

What's Changed

• Add support for doc_only attribute in confs and swregs by @arturum1 in #969
• fix(ipxact): Ignore confs with doc_only=True by @arturum1 in #970
• [ipxact_gen] added data_if to core and file name by @AndreMerendeira in #972

Full Changelog: V0.8...V0.82

V0.8

What's Changed

• Use Nix import instead of symlink by @arturum1 in #925
• fix(xsim): variables for remote simulation by @P-Miranda in #957
• fix(fpga): connect rstn wire to 1st interface by @P-Miranda in #961
• fix(regfile): replace regfile_t2p by regfile_at2p by @P-Miranda in #963
• Ipxact fix by @AndreMerendeira in #964
• feat(nco, axis): fix NCO, AXIS IN, AXIS OUT by @P-Miranda in #965

Full Changelog: V0.73...V0.8

V0.73

What's Changed

• Add iob_tasks equivalent for verilator; Update verilator testbench and csr_gen.py. by @arturum1 in #858
• fix(misc): wrapper extmem wires, remove latch by @P-Miranda in #857
• feat(nco): add nco module, minor fixes by @P-Miranda in #859
• Small fixes for lib modules and verilator testbench. by @arturum1 in #861
• chore(CACHE): Update CACHE submodule. by @arturum1 in #871
• fix(nix): Add missing gcc and libcap packages by @arturum1 in #876

Full Changelog: v0.72...V0.73

v0.72

What's Changed

• [apb] fixed apb converter and desconverter by @AndreMerendeira in #715
• [apb2iob] removed unused signals by @AndreMerendeira in #716
• [utils] added circular shift by @AndreMerendeira in #717
• [bfifo][pack/unpack] linting and formatting by @AndreMerendeira in #720
• [bfifo] fixed write operation by @AndreMerendeira in #724
• Add Nix packages for Linux; Add minicom configuration file. by @arturum1 in #722
• [module,py] fixed adding version and generating conf_h when no swregs by @AndreMerendeira in #726
• used localparams for constants by @AndreMerendeira in #727
• feat(is_system): Add is_system attribute to iob_module by @arturum1 in #728
• Linting and CSR fixes by @AndreMerendeira in #729
• [pack/unpack] added missing signal extension by @AndreMerendeira in #731
• Verilator fix by @jjts in #732
• Iob if by @AndreMerendeira in #734
• [apb2iob] removed rvalid testing by @AndreMerendeira in #737
• Fix apb by @jjts in #738
• Ipxact gen by @AndreMerendeira in #739
• Added fpga_list feature. Now only fpga's files in this liist will be copied by @AndreMerendeira in #740
• fix(if_gen): Fix bug in 'bus_size' argument by @arturum1 in #741
• [ipxact] macros are now ignored by @AndreMerendeira in #742
• Changed fpga_list to board_list by @AndreMerendeira in #743
• Added a try catch around get_build_dir otherwise error could delete entire project by @zettasticks in #745
• [create_wrapper_files] interconnect files only added if board folder exists in core by @AndreMerendeira in #744
• [ug] fake parameters are now placed in a list instead of the confs table by @AndreMerendeira in #747
• feat(iob_timer): add Timer linux drivers and user program example by @P-Miranda in #746
• fix(setup.mk): Exit with error when get_build_dir command fails. by @arturum1 in #748
• feat(drivers): improve iob_timer drivers to use sysfs; remove linux header code from python scripts by @P-Miranda in #758
• removed the sram reg defenition and switched to iob_reg by @Vasco-Luz in #770
• reset of the error by @Vasco-Luz in #771
• fix: update with @arturum1 fork by @P-Miranda in #774
• [asym_converter] fixed rdata changing without a read by @AndreMerendeira in #779
• [ipxact_gen] fixed module name by @AndreMerendeira in #780
• [iob_soc_utils.py] added search for scripts directory by @AndreMerendeira in #781
• [iob_soc_utils.py] fixed scripts copy by @AndreMerendeira in #786
• memwrap all commits by @Vasco-Luz in #791
• update memwrap by @Vasco-Luz in #795
• Memwrap by @jjts in #796
• feat(python): add mypy type checking to iob-soc setup by @P-Miranda in #799
• xcellium fix by @Vasco-Luz in #812
• removed memories and changed purposes of some submodules by @Vasco-Luz in #817
• fix(setup): clean [corename]_V* pattern by @P-Miranda in #831
• added yosys-abc and volare,fix syntax error ,end synthesys with genus by @Vasco-Luz in #828
• [iob_module] re-written _run_setup_files to import and run modules i… by @AndreMerendeira in #832
• Changed from hardcoded to dinamic io inside memwrap.v related to iob-soc instance. by @Vasco-Luz in #833
• [Artix US+] added board support for fpga-build by @AndreMerendeira in #841
• fix(CI): update checkout action to use node 20 by @P-Miranda in #839
• added a choice of synthesiser and added yosys synthesis by @Vasco-Luz in #849
• Added IOb-KU15P board support by @AndreMerendeira in #852
• [boards] added IOb-AU20P support by @AndreMerendeira in #853
• [fpga] fixed IOb-KU15P part by @AndreMerendeira in #854
• Merge eth_simulation into main by @P-Miranda in #856

Full Changelog: V0.71...v0.72

Interface stabilization

This release stabilizes the IOb native interface to connect the processor to the peripherals. The semantic is close to the AXI Lite handshake protocol, where the valid signal must not depend on the ready signal, and the ready signal may or may not depend on the valid signal. The registration of outputs is now mandatory. Consecutive reads or writes are possible, enabling pipelining. However, since the valid and r_ready_ signals are used both for reading and writing, and the ready output on the slave must be registered, changing from reads to writes or vice-versa needs a dead cycle in between. Many hardware modules have been improved or added; the iob_timer peripheral and the truly asymmetric iob_bfifo components are highlighted. The mkregs.py script that automatically inserts control and status registers in peripherals has been upgraded to support external IOb, AXI Lite, or AMBA APB interfaces. The suffixes _i and _o have been added to many module IOs to improve readability but may need to be added in some modules.

What's Changed

• Fix axi_m_port interface; Fix iob_soc_create_system.py; Update submodules. by @arturum1 in #608
• feat(LIB): fix LIB module tests; add CI job by @P-Miranda in #610
• fix(quartus): run timing.tcl once, report names by @P-Miranda in #613
• feat(fpga): add fpga test target, update CI to run fpga-test by @P-Miranda in #615
• Allow override of N_SLAVES macro by subclasses; Update axi_m_port part select script. by @arturum1 in #614
• [LIB] fixed spyglass and alint tcl by @AndreMerendeira in #616
• fix(CI): run individual fpga tests by @P-Miranda in #617
• fix(SWREG): _ADDR as macro address; remove unused _rvalikd_rd signal by @P-Miranda in #619
• [mkregs] removed unused pc by @AndreMerendeira in #620
• feat(test): upgrade tests by @P-Miranda in #624
• unify test and run targets by @jjts in #622
• fix(syn): rvalid_nxt in swreg_gen is wire by @P-Miranda in #625
• [BREAKING] Add core name prefix to *_conf.h macros. by @arturum1 in #627
• Remove Tester references from *_build.mk files. by @arturum1 in #628
• fix(axil2iob): register axil_bvalid_nxt by @P-Miranda in #633
• [cov] removed _CSR_IF.v from dut in xcelium.mk by @AndreMerendeira in #635
• fix(netlist): read .sdc from hw/fpga/src by @P-Miranda in #636
• fix(edge_detect) by @P-Miranda in #641
• [iob_soc] removed [width-1:0] in for width=1 by @AndreMerendeira in #640
• Fix Simulation with QuestaSim; Fix constant board grab timeout on FPGA. by @PedroAntunes178 in #639
• [hw][mkregs] added missing parenthesis. by @AndreMerendeira in #642
• [mkregs] removed unused signal by @AndreMerendeira in #644
• feat(str): add strncat implementation by @P-Miranda in #643
• Added FPU units, fix some errors from verilator in other units by @zettasticks in #645
• fix(sw): correct firmware size on USE_EXTMEM by @P-Miranda in #646
• fix(sw): check USE_EXTMEM variable by @P-Miranda in #647
• [prog.tcl] added error catch to commands by @AndreMerendeira in #648
• Remove the flows attribute. Move bsp.vh and bsp.h to the src/ directory. by @arturum1 in #651
• feat(netlist): add netlist support by @P-Miranda in #650
• Optimize console efficiency during simulation. by @arturum1 in #653
• iob_soc_create_system.py (update): by @PedroAntunes178 in #652
• Console: activating terminal non-canonical mode when necessary. by @PedroAntunes178 in #654
• [WIP] Ethernet by @arturum1 in #655
• update Quartus build.tcl to include fpga/src/$NAME.sdc file by @arturum1 in #656
• feat(ethernet): Remove PHY reset logic from wrappers. by @arturum1 in #658
• fpga/Makefile, console.py: pass GRAB_TIMEOUT value; call python3 instead of python. by @PedroAntunes178 in #657
• fix(hw): add _i and _o sufixes to module ports by @P-Miranda in #669
• noncanonical.py: fix compatibility with IObundle servers (older Python). by @PedroAntunes178 in #670
• fix(mk_configuration): Don't create *_params.vs if there are no parameters. by @arturum1 in #672
• Merge iob-soc/main branch; Update mk_configuration.py. by @arturum1 in #674
• feat: rstn branch, iob_interface Readme by @P-Miranda in #676
• fix(soc_interconnect): custom clk arst signals by @P-Miranda in #677
• fix(fpga): cyclonev fpga wrapper, reset_sync by @P-Miranda in #678
• Merge 'main' and 'enet' branches into 'edge_detect' by @arturum1 in #679
• Edge detect by @jjts in #681
• console (update): by @PedroAntunes178 in #680
• fix(hw): distinct signals for sync regs by @P-Miranda in #682
• Fix module setup order; Only setup flows for top module. by @arturum1 in #683
• [lint] linted fifo_sync, edge_detect, regfile_t2p and sync by @AndreMerendeira in #684
• [edge_detect] detected_prev wire now is only generated inside generate by @AndreMerendeira in #685
• [regfile_t2p] expressions in ports are not allowed by @AndreMerendeira in #686
• [regfile_t2p] fixed missing DATA_W from r_data wire by @AndreMerendeira in #687
• Add configurable build directory; Ethernet-related fixes. by @arturum1 in #688
• fix(pc_emul): Allow configurable pc-emul settings; Update README. by @arturum1 in #689
• Add ethernet FAST IO constraints for cyclonev by @arturum1 in #690
• [module.py] changed rw_overlap default to False by @AndreMerendeira in #692
• Generate alt_ddr3.qsys based on number of extmem connections. by @arturum1 in #693
• Console (fix): Only close tb_read if initialized. by @PedroAntunes178 in #694
• Fix bug in compute_addr of mkregs.py when rw_overlap=False by @arturum1 in #695
• [iob_tasks] fixed iob_read/write not blocking when ready=0 by @AndreMerendeira in #697
• Fix bug in read_next signal of axis2axi_in module by @arturum1 in #698
• [axis2fifo][fifo2axis] reordered ports by @AndreMerendeira in #699
• Reorder variable definitions of fpga_build.mk by @arturum1 in #704
• feat(timer): add iob_timer as LIB module by @P-Miranda in #705
• Added registers to swreg CSR-IF outputs and to axis outputs by @AndreMerendeira in #703
• [mkregs] auxiliary wires are now only included when not using iob IF by @AndreMerendeira in #707
• [mkregs] csr-if converters are now automatically added to hw code by @AndreMerendeira in #709

New Contributors

• @zettasticks made their first contribution in #645

Full Changelog: V0.70...V0.71

Python Automation

This release introduces Python scripts to automate the creation of a build directory with all the necessary files and build makefiles for running emulation, RTL simulation, and FPGA. There are also significant advances in the automatic creation of Control and Status Register (CSR) files, comprising both the hardware and bare-metal software and in generating standard interfaces such as AXI4 and AMBA. The UART and LIB submodules have been integrated into IOb-SoC, which reduces the use of git submodules and associated problems.

What's Changed

• Uartdev merged to verilator and the relevant pushes applied to finish up the rest of the verilator testbench by @slahiruk in #107
• Verilator updates to wrapper by @slahiruk in #108
• Verilator changes to include wrapper by @slahiruk in #110
• Verilator new changes by @slahiruk in #111
• Verilator, add cpu_tasks.v after merging master by @slahiruk in #112
• Verilator by @PedroAntunes178 in #195
• Verilator by @PedroAntunes178 in #197
• Master merge by @PedroAntunes178 in #234
• Verilator by @PedroAntunes178 in #235
• Verilator by @PedroAntunes178 in #236
• Verilator by @PedroAntunes178 in #269
• Verilator by @PedroAntunes178 in #274
• update CACHE and MEM submodules; update sources according new version of the submodules by @JDLopes in #293
• fix(test): Update test.expected files by @P-Miranda in #294
• update(MEM): Update MEM with python3 by @P-Miranda in #295
• Update submodules, fix simulation by @P-Miranda in #296
• fix(doc): Update documentation path by @P-Miranda in #297
• Fix simulation, update test.expected, update UART submodule by @P-Miranda in #299
• fix(test): Better cleanup of extra files, Update expected logs for test by @P-Miranda in #301
• Improve test.expected logs, Update docs and README by @P-Miranda in #303
• fix USER variable when execute queue-out-remote in FPGA Makefiles by @JDLopes in #304
• Update submodules and documentation by @P-Miranda in #305
• update(doc): new steps to add timer by @P-Miranda in #306
• copy VCD file in case of Ctrl+C is pressed by @JDLopes in #309
• add(submodules): Single level submodule dependency by @P-Miranda in #310
• fix(AXI): Fix path to AXI submodule; Update UART by @P-Miranda in #311
• Verilator by @PedroAntunes178 in #312
• Verilator by @PedroAntunes178 in #313
• Verilator by @PedroAntunes178 in #314
• switched to devel for future work from now on by @microSharjeel in #318
• Verilator by @PedroAntunes178 in #319
• Verilator by @PedroAntunes178 in #320
• changes in targets ....combined and removed by @microSharjeel in #322
• changes to add sp ram in sram.v after merge with devel by @microSharjeel in #323
• changes for addition of USE_SPRAM by @microSharjeel in #324
• Verilator by @PedroAntunes178 in #328
• Verilator devel by @PedroAntunes178 in #329
• fix .sdc file generation for ASIC; rename ASIC report files extention; update all submodules; update sources by @JDLopes in #332
• update system.v and system_tb.v targets; update system_core_tb.v file; update CACHE submodule by @JDLopes in #333
• update UART submodule by @JDLopes in #335
• Verilator by @PedroAntunes178 in #334
• Updated with iob-soc devel branch; Initial version of modelsim working by @P-Miranda in #336
• update LIB submodule; fix documents generation; update PDFs and test.expected files by @JDLopes in #337
• INIT_MEM=0 should be set manually by @PedroAntunes178 in #338
• Verilator by @PedroAntunes178 in #341
• merge with iob-soc/verilator; remove coco_tb by @JDLopes in #342
• minor improvements; update AXI submodule by @JDLopes in #343
• fix .gitignore file; add verilator to simulation tests; cleanup simulation.mk file; remove debug code lines from testbenches; fix console; add test.expected file for verilator; add ifdef VCD to verilator testbench; update test.expected files; centralize console call; update LIB submodule; update synscript.tcl according new LIB version by @JDLopes in #344
• fix remote simulation by @JDLopes in #345
• fix console when receive file name via FPGA; remove dummy test target; update test.expected files for FPGAs; cleanup clean targets for FPGAs by @JDLopes in #346
• Devel by @PedroAntunes178 in #347
• update test.expected for Verilator by @JDLopes in #354
• update test.expected file for product brief by @JDLopes in #356
• update UART submodule by @JDLopes in #357
• fix kill console both on simulation and FPGA run by @JDLopes in #359
• Fixed bug that caused the verilator testbench to not pass the second test by @PedroAntunes178 in #360
• fix INIT_MEM for simulation when it's not set on the command; fix console kill process by @JDLopes in #361
• Removed fseek and truncate from console and testbench. by @PedroAntunes178 in #363
• update AXI submodule; update sources according new AXI version by @JDLopes in #364
• update AXI submodule by @JDLopes in #365
• change default serial port to connect to FPGAs by @JDLopes in #366
• kill console in case of a trap by @JDLopes in #368
• fix(console): usage error | fix(sw): Warning for possible misaligned accesses by @P-Miranda in #370
• fix console to print non-ascii characteres like copyright by @JDLopes in #371
• fix kill console when FPGA run is interrupted; move define in CycloneV Makefile by @JDLopes in #373
• Fix ser.read(file_size) would not receive full s_fw.bin; by @PedroAntunes178 in #374
• fix reset in testbench; remove unused signal in top_system.v file for AES-KU040-DB-G FPGA; update MEM submodule by @JDLopes in #377
• feat: changes to support ethernet core integration by @P-Miranda in #378
• fix(fpga): special handling of TEST_LOG by @P-Miranda in #379
• Call Console from PC-emul Makefile. by @PedroAntunes178 in #380
• Fix fpga-test, update docs by @P-Miranda in #382
• remove dummy target from quartus.mk by @JDLopes in #383
• Improve drivers, Update LIB UART by @P-Miranda in #385
• Simplify system_core_tb.v; Now Icarus also uses system_top.v by @PedroAntunes178 in #386
• Fix bug in firmware.S by @arturum1 in #387
• fix baudrate setting for pc-emul, simulation, FPGA and ASIC; set serial port timeout to None in console; change default baudrate to 115200 in config.mk by @JDLopes in #388
• Fix tests by @JDLopes in #390
• fix tests by @JDLopes in #391
• Minor improvements by @JDLopes in #393
• Minor improvements by @jjts in #394
• feat(doc): Review README and presentation by @P-Miranda in #395
• feat(doc): update test.expected by @P-Miranda in #396
• fix variable name by @JDLopes in #397
• feat(LIB): update LIB, UART submodules by @P-Miranda in #398
• Add multi-instance capability; Remove 'pi...

V0.6

What's Changed

• started DE10 board support development by @AndreMerendeira in #113
• updated gitignore to ignore synthesis files in DE10 and ku040 boards by @AndreMerendeira in #114
• minor improvement (clean target) by @JDLopes in #115
• update CACHE submodule by @JDLopes in #117
• improve Makefiles by @JDLopes in #120
• revert console Makefile by @JDLopes in #124
• Fixed DE10-Lite frequency and baud-rate. Added missing BOARD_USER. Fixed DE10-Lite top_system.tcl by @AndreMerendeira in #125
• update UART submodule by @JDLopes in #128
• Added xilinx reports generation by @pedrompt97 in #129
• update ASIC framework to use new Makefiles; change FIRM_ADDR_W and SRAM_ADDR_W default values; fix bug by @JDLopes in #130
• Makefile revamp working for DE10 FPGA by @P-Miranda in #132
• improve asic Makefile; update UART submodule by @JDLopes in #133
• fixed DE10 support (IS_CYCLONE was 1) by @AndreMerendeira in #134
• Makefile revamp by @AndreMerendeira in #135
• fix Makefile clean targets; add missing target to .PHONY list in simulation.mk Makefile segment by @JDLopes in #137
• improve xcelium Makefile by @JDLopes in #138
• improve documentation Makefiles by @JDLopes in #139
• Added git password cache to README by @P-Miranda in #140
• update presentation: update example firmware code and its output by @JDLopes in #141
• add a slide with the run on FPGA output by @JDLopes in #142
• fix Makefiles clean target; add missing command for transferring FPGA log files to the local machine; fix pb document generation; minor corrections to the README.md file; update UART submodule by @JDLopes in #143
• implement lock files when using FPGAs; update test.expected file for xcelium simulator by @JDLopes in #144
• update UART submodule by @JDLopes in #145
• improve lock and unlock targets by @JDLopes in #147
• kill remote tools when Ctrl+C is typed in by @JDLopes in #148
• fix unlock fpga, when Makefiles are run from BOARD_SERVER by @JDLopes in #149
• fix run target for FPGAs by @JDLopes in #150
• implement queue for using FPGAs; add variables for manage FPGA loads by @JDLopes in #152
• changed soffice to libreoffice by @AndreMerendeira in #151
• switch append file for overwrite file by @JDLopes in #154
• fix Vivado path by @JDLopes in #156
• updated submodule UART by @DiogoFausto in #157
• fix misspelled command by @JDLopes in #158
• remove lock files for FPGAs; change FPGA log file content; fix board path by @JDLopes in #161
• uncomment create_clock in xdc file; add missing dependencies to system.v and system_tb.v targets by @JDLopes in #175
• update UART submodule; use _be memories in sram module; update CACHE submodule; update hardware.mk; update test.expected files for simulators and FPGAs; merge with branch master by @JDLopes in #177
• fix presentation Makefile: add missing variables by @JDLopes in #178
• Asic by @microSharjeel in #182
• fix Makefile: add missing variable definitions; update UART submodule by @JDLopes in #183
• add framework to generate ASIC memories; update .gitignore file by @JDLopes in #190
• Readme for OpenLane by @microSharjeel in #193
• update .expected files; use --delete flag on clean-remote targets only; fix .gitignore file; minor improvements in FPGAs' Makefiles; merge with iob-soc/master by @JDLopes in #199
• update CACHE submodule; update sources according to the new CACHE submodule; remove asic-mems target from root Makefile; fix DDR_ADDR_W define in asic.mk by @JDLopes in #200
• define MEM_DIR in system.mk; update paths in hardware.mk; add targets to generate memories' wrappers; update CACHE submodule by @JDLopes in #202
• fix targets for memory wrappers; change shell script permissions; fix sram.v generation for ASIC; improve asic.mk; cleanup datasheet files from ASIC memories; transfer ASIC reports from server to local machine; use CASE variable to filter libraries to use on synthesis for ASIC; update CACHE submodule; update sources according new submodule; rename XMSIM_SERVER and XMSIM_USER variables to CADENCE_SERVER and CADENCE_USER by @JDLopes in #203
• move test.log for FPGAs from console to FPGA directory; remove dummy character by @JDLopes in #204
• fix clean-testlog target by @JDLopes in #205
• Python3 by @P-Miranda in #207
• major ASIC Makefiles revamp; change initial.v file name to initial_sram.v; update .gitignore file; update root Makefile; update simulation.mk; update CACHE and UART submodules by @JDLopes in #206
• add missing axi signals for full AXI4-full protocol support; merge with iob-soc/master by @JDLopes in #209
• fix .queue and .load files' permissions by @JDLopes in #212
• Axi4 signals missingmerge with iob-soc/master by @JDLopes in #213
• README for OpenLane and OpenRAM by @microSharjeel in #221
• update CACHE submodule; update sources according to new CACHE by @JDLopes in #222
• Include submodules based on corename instead of submodule folder name by @arturum1 in #210
• fix ASIC RAM initialization; update CACHE submodule; merge with iob-soc/master by @JDLopes in #223
• fix merge with iob-soc/master by @JDLopes in #224
• Asic by @microSharjeel in #225
• fix ASIC tests' targets; change ASIC framework for synthesize iob-soc with DDR access; fix ASIC memories' targets; update UART and CACHE submodules by @JDLopes in #226
• update test.expected file for xcelium simulator by @JDLopes in #227
• Makefile for OpenRAM/OpenLane. OpenRAM make rule added by @microSharjeel in #228
• Create myconfig.py by @microSharjeel in #230
• Asic by @microSharjeel in #231
• Asic by @microSharjeel in #232
• make ASIC simulation memories' files depend on technology node; add ifdef SRAM_INIT in initial_dp_ram.v file to avoid simulation warnings; move hex_split and makehex scripts from iob-soc to iob-mem; remove unused python scripts; update CACHE submodule; update source files; merge with iob-soc/master by @JDLopes in #237
• Addresses #146 by @P-Miranda in #238
• Changes in Makefile for OpenLane Docker start by @microSharjeel in #239
• update CPU submodule; update sources by @JDLopes in #240
• rename SUBMODULES_TMP to SUBMODULES by @JDLopes in #242
• Console/TB waits for ACK before sending file by @AndreMerendeira in #243
• updated UART by @AndreMerendeira in #244
• minor changes in hardware.mk; update CACHE, LIB, MEM, TEX and UART submodules by @JDLopes in #246
• update CACHE, CPU and INTERCON submodules by @JDLopes in #247
• update CACHE and UART submodules by @JDLopes in #248
• Added target for openlane flow by @microSharjeel in #245
• temp folder and copy target for testing by @microSharjeel in #250
• add ASIC variable for generate documents; include asic_results.tex file if ASIC=1; remove TEX and INTERCON submodules; update UART submodule by @JDLopes in #251
• Changes made for OpenLane and now it is working by @microSharjeel in #252
• up...

V0.5

Full Changelog: V0.4...V0.5