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Pulser server
The phase coherent DDS boards maintain phase coherence of the generated RF signal if the generated frequency is kept constant. For example, if the pulse sequence has two back-to-back pulses of the same frequency, they will have the same phase as measured relative to an external clock. Any change of frequency destroys phase coherence.
- Simplified clearing pmt counts when either the count rate or the mode is changed. Now, after every change first two counts from the FPGA are removed. This removed all spikes.
- Bug fix: InCommunication DeferredLock was not used while using the 'output' setting. This led to freezes while rapidly turning pulser off and on.
- Added resetstepDuration parameter to the HardwareConfiguration. This controls the duration of the TTL pulses used to advance and reset the DDS boards. Should be set to 2.
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Adds the ability to have an optical 2nd PMT, and DAC. (Merge from Dylan, CCT).
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Fixed bug of not programming remaining pulses if a 0-length dds pulse encountered.
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Syntax changed required for simpifying GUIs:
self.pulser.output(name, False)
instead of
self.pulser.select_channel(name)
self.pulser.output(False)
- DDS Lock Behavior Change:
The dds lock is activated when any pulse sequence is programmed. It can now be cleared only when the pulse sequence is completed or a a new setting called clear_dds_lock is called. This setting has to be called at the end of each experiment that requires to pulser even if the measurement is interrupted. This means one needs a try, except block and run the experiment in a console where it is sensitive to keyboard interrupt.