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Pulser server
- provide some examples, files
- readout
- time tags
The phase coherent DDS boards maintain phase coherence of the generated RF signal if the generated frequency is kept constant. For example, if the pulse sequence has two back-to-back pulses of the same frequency, they will have the same phase as measured relative to an external clock. Any change of frequency destroys phase coherence. As long as the frequency is kept constant, however, the phase can be set to an arbitrary value for every pulse.
Switching the frequency on the DDS board takes several microseconds but changing the amplitude is immediate. Therefore to achieve switch to the new pulse conditions with no delays, the frequency has to be programmed first, and then the amplitude should be changed at the start time of the pulse. A 6 microsecond difference between frequency and amplitude programming should be sufficient.
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Line triggering offset is limited to (0,15000) \mus. Due to a discrepancy between the real clock and the pulser clock, the maximum is slightly less than 1 / 60 Hz.
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The minimum duration of a pulse is 160ns, which is 4 pulser clock cycles. The minimum duration of a gap between pulses is the same. Beyond the minimum, the resolution can be set in multiples of 40ns.
- new bit file pulser_2013_06_05.bit which fixes bug of not always reprogramming the pulser with a new sequence
- removed DAC settings
- extra debugging settings
- Updated test file to match the latest pulse sequence inheritance
- Plotting works for local coherent channels
- Changed the limits for line triggering offset to (0,15000) \mus. Due to a discrepancy between the real clock and the pulser clock, the maximum is slightly less than 1 / 60 Hz.
- DDS Hardware settings distinguish between remote dds boards and phase coherent dds boards. This allows for phase coherent boards that are local. See parameters
phase_coherent_modelandremoteinHardwareConfiguration.py.sample.
- Ability to do Line Triggering
- Simplified clearing pmt counts when either the count rate or the mode is changed. Now, after every change first two counts from the FPGA are removed. This removed all spikes.
- Bug fix: InCommunication DeferredLock was not used while using the 'output' setting. This led to freezes while rapidly turning pulser off and on.
- Added resetstepDuration parameter to the HardwareConfiguration. This controls the duration of the TTL pulses used to advance and reset the DDS boards. Should be set to 2.
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Adds the ability to have an optical 2nd PMT, and DAC. (Merge from Dylan, CCT).
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Fixed bug of not programming remaining pulses if a 0-length dds pulse encountered.
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Syntax changed required for simpifying GUIs:
self.pulser.output(name, False)
instead of
self.pulser.select_channel(name)
self.pulser.output(False)
- DDS Lock Behavior Change:
The dds lock is activated when any pulse sequence is programmed. It can now be cleared only when the pulse sequence is completed or a a new setting called clear_dds_lock is called. This setting has to be called at the end of each experiment that requires to pulser even if the measurement is interrupted. This means one needs a try, except block and run the experiment in a console where it is sensitive to keyboard interrupt.