zephyrproject-rtos · lucien-nxp · Nov 7, 2024 · Nov 7, 2024 · Nov 7, 2024 · Nov 14, 2024
diff --git a/.github/workflows/west_cmds.yml b/.github/workflows/west_cmds.yml
@@ -66,7 +66,7 @@ jobs:
     - name: install pytest
       run: |
         pip3 install wheel
-        pip3 install pytest west pyelftools canopen natsort progress mypy intelhex psutil ply pyserial
+        pip3 install pytest west pyelftools canopen natsort progress mypy intelhex psutil ply pyserial anytree
     - name: run pytest-win
       if: runner.os == 'Windows'
       run: |

diff --git a/arch/arm/include/cortex_m/exception.h b/arch/arm/include/cortex_m/exception.h
@@ -258,7 +258,7 @@ static ALWAYS_INLINE void z_arm_set_fault_sp(const struct arch_esf *esf, uint32_
 	}
 #endif /* CONFIG_FPU && CONFIG_FPU_SHARING */
 
-#ifndef CONFIG_ARMV8_M_MAINLINE
+#if !(defined(CONFIG_ARMV8_M_MAINLINE) || defined(CONFIG_ARMV8_M_BASELINE))
 	if ((esf->basic.xpsr & SCB_CCR_STKALIGN_Msk) == SCB_CCR_STKALIGN_Msk) {
 		/* Adjust stack alignment after PSR bit[9] detected */
 		z_arm_coredump_fault_sp |= 0x4;

diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4.dts b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4.dts
@@ -9,13 +9,28 @@
 
 #include <infineon/cat1a/legacy/psoc6_cm4.dtsi>
 #include "cy8ckit_062_ble_common.dtsi"
+#include "cy8ckit_062_ble_cy8c6347-pinctrl.dtsi"
 
 / {
 	model = "Cypress PSoC6 BLE Pioneer Kit";
 	compatible = "cypress,cy8c6xx7_cm4", "cypress,psoc6";
 
+	aliases {
+		uart-6 = &uart6;
+	};
+
 	chosen {
 		zephyr,sram = &sram2;
 		zephyr,flash = &flash1;
+		zephyr,console = &uart6;
+		zephyr,shell-uart = &uart6;
 	};
 };
+
+&uart6 {
+	status = "okay";
+	current-speed = <115200>;
+
+	pinctrl-0 = <&p13_0_scb6_uart_rx &p13_1_scb6_uart_tx>;
+	pinctrl-names = "default";
+};
diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.overlay b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.overlay
diff --git a/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig b/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig
@@ -17,9 +17,6 @@ CONFIG_UART_CONSOLE=y
 # Enable UART driver
 CONFIG_SERIAL=y
 
-# Enable GPIO driver
-CONFIG_GPIO=y
-
 # Enable clock controller
 CONFIG_CLOCK_CONTROL=y
 

diff --git a/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble_defconfig b/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble_defconfig
@@ -18,9 +18,6 @@ CONFIG_UART_CONSOLE=y
 # Enable UART driver
 CONFIG_SERIAL=y
 
-# Enable GPIO
-CONFIG_GPIO=y
-
 # Enable clock controller
 CONFIG_CLOCK_CONTROL=y
 

diff --git a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig
@@ -18,9 +18,6 @@ CONFIG_UART_CONSOLE=y
 # Enable UART driver
 CONFIG_SERIAL=y
 
-# Enable GPIO driver
-CONFIG_GPIO=y
-
 # Enable clock controller
 CONFIG_CLOCK_CONTROL=y
 

diff --git a/boards/lilygo/ttgo_lora32/doc/index.rst b/boards/lilygo/ttgo_lora32/doc/index.rst
@@ -1,7 +1,4 @@
-.. _ttgo_lora32:
-
-Lilygo TTGO LoRa32
-##################
+.. zephyr:board:: ttgo_lora32
 
 Overview
 ********
@@ -18,13 +15,6 @@ It's available in two versions supporting two different frequency ranges and fea
 
 Some of the ESP32 I/O pins are accessible on the board's pin headers.
 
-.. figure:: img/ttgo_lora32.webp
-        :align: center
-        :alt: Lilygo TTGO LoRa32 module
-        :width: 400 px
-
-        Lilygo TTGO LoRa32 module
-
 Functional Description
 **********************
 

diff --git a/boards/lilygo/ttgo_t8c3/doc/index.rst b/boards/lilygo/ttgo_t8c3/doc/index.rst
@@ -1,7 +1,4 @@
-.. _ttgo_t8c3:
-
-Lilygo TTGO T8-C3
-#################
+.. zephyr:board:: ttgo_t8c3
 
 Overview
 ********
@@ -17,12 +14,6 @@ It features the following integrated components:
 - JST GH 2-pin battery connector
 - LED
 
-.. figure:: img/ttgo_t8c3.webp
-   :align: center
-   :alt: TTGO T8-C3
-
-   Lilygo TTGO T8-C3
-
 Functional Description
 **********************
 This board is based on the ESP32-C3 with 4MB of flash, WiFi and BLE support. It

diff --git a/boards/nxp/mimxrt700_evk/CMakeLists.txt b/boards/nxp/mimxrt700_evk/CMakeLists.txt
@@ -0,0 +1,28 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if(CONFIG_BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU0 OR CONFIG_BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU1)
+  zephyr_library()
+  zephyr_library_sources(board.c)
+endif()
+
+if(CONFIG_NXP_IMXRT_BOOT_HEADER)
+  if(NOT ((DEFINED CONFIG_BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU0)
+  OR (DEFINED CONFIG_BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU1)))
+  message(WARNING "It appears you are using the board definition for "
+    "the MIMXRT7xx-EVK, but targeting a custom board. You may need to "
+    "update your flash configuration block data")
+  endif()
+  # Include flash configuration block for RT7xx EVK from NXP's HAL.
+  # This configuration block may need modification if another flash chip is
+  # used on your custom board. See NXP AN13304 for more information.
+  zephyr_compile_definitions(BOOT_HEADER_ENABLE=1)
+  zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024)
+  set(RT7XX_BOARD_DIR
+    "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/mimxrt700evk")
+  zephyr_library_sources(${RT7XX_BOARD_DIR}/flash_config/flash_config.c)
+  zephyr_library_include_directories(${RT7XX_BOARD_DIR}/flash_config)
+endif()
diff --git a/boards/nxp/mimxrt700_evk/Kconfig.mimxrt700_evk b/boards/nxp/mimxrt700_evk/Kconfig.mimxrt700_evk
@@ -0,0 +1,7 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_MIMXRT700_EVK
+	select SOC_MIMXRT798S_CM33_CPU0 if BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU0
+	select SOC_MIMXRT798S_CM33_CPU1 if BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU1
+	select SOC_PART_NUMBER_MIMXRT798SGFOA