arch: arm: cortex_m: pm_s2ram: add support for ARMv6-M and ARMv7-M #76412
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Rebased on main to trigger CI again (failure was due to faulty code in |
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I've done a very (limited) test on armv7-M (m4) and it seems to work. I can't do a full test as we are still working on fully implementing s2ram for our platform, which is the qn9090 soc from NXP. |
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I apologize for the delay in providing a review. I am not familiar with all the registers saved/restored in this module. Some of the things that confuse me a bit are for example saving & restoring EPSR which cannot be accessed by MSR/MRS, and IPSR which is read only. |
No problem 😄
I agree with you that some things performed by this module appear incorrect or useless, but I kept it as-is to not introduce functional changes. I'm fine with removing them though. I am preparing a reworked version of this PR to make review easier and address the points raised by @HesselM ... |
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Patch v3 (rebased on main, just in case...)
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Noticed what seems like an error introduced in #77277 when rebasing: https://github.com/zephyrproject-rtos/zephyr/pull/77277/files#r1732765743 |
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@HesselM, can you approve this PR if this looks good to you. |
Remove all xPSR-related registers from struct __cpu_context, and the associated save/restore code in S2RAM code, as they are not needed: * EPSR and IPSR are read-only - they cannot be "restored" * Bits N, V, Z, C, V, Q, and GE (if DSP Extension is implemented) of APSR could be restored, but this is not needed as the AAPCS indicates these bits to be "undefined on entry to or return from a public interface" Signed-off-by: Mathieu Choplain <[email protected]>
Use macros to wrap the interaction between the assembly code and the struct __cpu_context. This helps making the assembly more readable. Signed-off-by: Mathieu Choplain <[email protected]>
Wrap the CPU register save/restore operations (GPR and special registers) in macros to make core logic simpler to follow. This is also a preparatory step to introduce ARMv6-M and ARMv7-M support. Signed-off-by: Mathieu Choplain <[email protected]>
Extend the ARM M-profile suspend-to-RAM implementation to be compatible with all versions of the M-profile supported by Zephyr: ARMv6-M, ARMv7-M, and ARMv8-M Baseline. Signed-off-by: Mathieu Choplain <[email protected]>
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Patch v2:
Builds with dummy PM implementation for STM32WB0x series (ARMv6M / Cortex-M0+) I did not incorporate any revert of 978e5b9 but wouldn't mind doing so. |
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Seems to work on M7 |
This PR makes the ARM implementation of suspend-to-RAM compatible with the ARMv6-M and ARMv7-M architectures.
Tested on Cortex-M0+ (ARMv6-M) with a minimal example that invokes
arch_pm_s2ram_suspenddirectly; CPU registers appear to be properly restored after resuming from the low-power mode.Not tested on ARMv7-M due to lack of hardware.