soc: atmel: fix wait state value

The datasheet specifies that 2 wait states are required at 48 MHz. Signed-off-by: Maksim Drachov <[email protected]>
zephyrproject-rtos · Sep 4, 2024 · e7e27f1 · e7e27f1
1 parent 689d1ed
commit e7e27f1
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/soc/atmel/sam0/common/soc_samc2x.c b/soc/atmel/sam0/common/soc_samc2x.c
@@ -17,8 +17,8 @@
 
 static void flash_waitstates_init(void)
 {
-	/* One wait state at 48 MHz. */
-	NVMCTRL->CTRLB.bit.RWS = NVMCTRL_CTRLB_RWS_HALF_Val;
+	/* Two wait state at 48 MHz. */
+	NVMCTRL->CTRLB.bit.RWS = NVMCTRL_CTRLB_RWS_DUAL_Val;
 }
 
 static void osc48m_init(void)