boards: xtensa: add M5Stack CoreS3 support

Initial support for M5Statck CoreS3 development board.

Signed-off-by: Zhang Xingtao <[email protected]>

boards/m5stack/m5stack_cores3/Kconfig.defconfig

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+# Copyright (c) 2024 Zhang Xingtao <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_M5STACK_CORES3_ESP32S3_PROCPU
+
+config HEAP_MEM_POOL_ADD_SIZE_BOARD
+	int
+	default $(UINT16_MAX) if WIFI && BT
+	default 51200 if WIFI
+	default 40960 if BT
+	default 4096
+
+endif # BOARD_M5STACK_CORES3_ESP32S3_PROCPU
+
+
+if BOARD_M5STACK_CORES3_ESP32S3_APPCPU
+
+config HEAP_MEM_POOL_ADD_SIZE_BOARD
+	default 256
+
+endif # BOARD_M5STACK_CORES3_ESP32S3_APPCPU

boards/m5stack/m5stack_cores3/Kconfig.m5stack_cores3

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+# M5Stack CoreS3 board configuration
+
+# Copyright (c) 2024 Zhang Xingtao <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_M5STACK_CORES3
+	select SOC_ESP32S3_WROOM_N16R8
+	select SOC_ESP32S3_PROCPU if BOARD_M5STACK_CORES3_ESP32S3_PROCPU
+	select SOC_ESP32S3_APPCPU if BOARD_M5STACK_CORES3_ESP32S3_APPCPU

boards/m5stack/m5stack_cores3/board.cmake

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+# SPDX-License-Identifier: Apache-2.0
+
+if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*")
+  set(OPENOCD OPENOCD-NOTFOUND)
+endif()
+find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH)
+
+include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

boards/m5stack/m5stack_cores3/board.yml

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+board:
+  name: m5stack_cores3
+  vendor: m5stack
+  socs:
+  - name: esp32s3

boards/m5stack/m5stack_cores3/doc/index.rst

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+.. _m5stack_cores3:
+
+M5Stack CoreS3
+##############
+
+Overview
+********
+
+M5Stack CoreS3 is an ESP32-based development board from M5Stack. It is the third generation of the M5Stack Core series.
+
+M5Stack CoreS3 features consist of:
+
+- ESP32-S3 chip (dual-core Xtensa LX7 processor @240MHz, WIFI, OTG\CDC functions)
+- PSRAM 8MB
+- Flash 16MB
+- LCD ISP 2", 320x240 pixel ILI9342C
+- Capacitive multi touch FT6336U
+- Camera 30W pixel GC0308
+- Speaker 1W AW88298
+- Dual Microphones ES7210 Audio decoder
+- RTC BM8563
+- USB-C
+- SD-Card slot
+- Geomagnetic sensor BMM150
+- Proximity sensor LTR-553ALS-WA
+- 6-Axis IMU BMI270
+- PMIC AXP2101
+- Battery 500mAh 3,7V
+
+.. figure:: img/m5stack_cores3.webp
+        :align: center
+        :alt: M5Stack-CoreS3
+        :width: 400 px
+
+        M5Stack CoreS3 module
+
+Start Application Development
+*****************************
+
+Before powering up your M5Stack CoreS3, please make sure that the board is in good
+condition with no obvious signs of damage.
+
+System requirements
+===================
+
+Prerequisites
+-------------
+
+Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command
+below to retrieve those files.
+
+.. code-block:: console
+
+   west blobs fetch hal_espressif
+
+.. note::
+
+   It is recommended running the command above after :file:`west update`.
+
+Building & Flashing
+-------------------
+
+Build and flash applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: m5stack_cores3/esp32s3/procpu
+   :goals: build
+
+The usual ``flash`` target will work with the ``m5stack_cores3`` board
+configuration. Here is an example for the :ref:`hello_world`
+application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: m5stack_cores3/esp32s3/procpu
+   :goals: flash
+
+The baud rate of 921600bps is set by default. If experiencing issues when flashing,
+try using different values by using ``--esp-baud-rate <BAUD>`` option during
+``west flash`` (e.g. ``west flash --esp-baud-rate 115200``).
+
+You can also open the serial monitor using the following command:
+
+.. code-block:: shell
+
+   west espressif monitor
+
+After the board has automatically reset and booted, you should see the following
+message in the monitor:
+
+.. code-block:: console
+
+   *** Booting Zephyr OS build vx.x.x-xxx-gxxxxxxxxxxxx ***
+   Hello World! m5stack_cores3/esp32s3/procpu
+
+
+Debugging
+---------
+
+ESP32-S3 support on OpenOCD is available upstream as of version 0.12.0.
+Download and install OpenOCD from `OpenOCD`_.
+
+ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additional chip. Only an USB cable connected to the D+/D- pins is necessary.
+
+Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32-S3`_.
+
+.. _`OpenOCD`: https://github.com/openocd-org/openocd
+.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/
+
+
+Related Documents
+*****************
+
+- `M5Stack CoreS3 official docs <http://docs.m5stack.com/en/core/CoreS3>`_
+- `M5Stack CoreS3 schematic <https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/K128%20CoreS3/Sch_M5_CoreS3_v1.0.pdf>`_ (PDF)
+

boards/m5stack/m5stack_cores3/m5stack_cores3-pinctrl.dtsi

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+/*
+ * Copyright (c) 2024 Zhang Xingtao <[email protected]>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
+#include <zephyr/dt-bindings/pinctrl/esp32s3-pinctrl.h>
+#include <zephyr/dt-bindings/pinctrl/esp32s3-gpio-sigmap.h>
+
+
+&pinctrl {
+	uart0_default: uart0_default {
+		group1 {
+			pinmux = <UART0_TX_GPIO43>;
+			output-high;
+		};
+		group2 {
+			pinmux = <UART0_RX_GPIO44>;
+			bias-pull-up;
+		};
+	};
+
+	spim2_default: spim2_default {
+		group1 {
+			pinmux = <SPIM2_MISO_GPIO35>,
+				 <SPIM2_SCLK_GPIO36>;
+		};
+		group2 {
+			pinmux = <SPIM2_MOSI_GPIO37>;
+			output-low;
+		};
+	};
+
+       spim3_default: spim3_default {
+                group1 {
+                        pinmux = <SPIM3_MISO_GPIO35>,
+                                 <SPIM3_SCLK_GPIO36>;
+                };
+                group2 {
+                        pinmux = <SPIM3_MOSI_GPIO37>;
+                        output-low;
+                };
+        };
+
+
+	i2c0_default: i2c0_default {
+		group1 {
+			pinmux = <I2C0_SDA_GPIO12>,
+				 <I2C0_SCL_GPIO11>;
+			bias-pull-up;
+			drive-open-drain;
+			output-high;
+		};
+	};
+
+	twai_default: twai_default {
+		group1 {
+			pinmux = <TWAI_TX_GPIO3>,
+				<TWAI_RX_GPIO4>;
+		};
+	};
+};

boards/m5stack/m5stack_cores3/m5stack_cores3_appcpu.dts

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+/*
+ * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/dts-v1/;
+
+#include <espressif/esp32s3/esp32s3_appcpu.dtsi>
+
+/ {
+	model = "M5Stack CoreS3 APPCPU";
+	compatible = "espressif,esp32s3";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,ipc_shm = &shm0;
+		zephyr,ipc = &ipm0;
+	};
+};
+
+&ipm0 {
+	status = "okay";
+};
+
+&trng0 {
+	status = "okay";
+};
+
+&flash0 {
+	status = "okay";
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* Reserve 60kB for the bootloader */
+		boot_partition: partition@1000 {
+			label = "mcuboot";
+			reg = <0x00001000 0x0000F000>;
+			read-only;
+		};
+
+		/* Reserve 1024kB for the application in slot 0 */
+		slot0_partition: partition@10000 {
+			label = "image-0";
+			reg = <0x00010000 0x00100000>;
+		};
+
+		/* Reserve 1024kB for the application in slot 1 */
+		slot1_partition: partition@110000 {
+			label = "image-1";
+			reg = <0x00110000 0x00100000>;
+		};
+
+		/* Reserve 256kB for the scratch partition */
+		scratch_partition: partition@210000 {
+			   label = "image-scratch";
+			   reg = <0x00210000 0x00040000>;
+		};
+
+		storage_partition: partition@250000 {
+			label = "storage";
+			reg = <0x00250000 0x00006000>;
+		};
+	};
+};

boards/m5stack/m5stack_cores3/m5stack_cores3_appcpu.yaml

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+identifier: m5stack_cores3/esp32s3/appcpu
+name: M5Stack CoreS3 APPCPU
+type: mcu
+arch: xtensa
+toolchain:
+  - zephyr
+supported:
+  - uart
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
+    - flash
+    - cpp
+    - posix
+    - watchdog
+    - logging
+    - kernel
+    - pm
+    - gpio
+    - crypto
+    - eeprom
+    - heap
+    - cmsis_rtos
+    - jwt
+    - zdsp
+vendor: m5stack

boards/m5stack/m5stack_cores3/m5stack_cores3_appcpu_defconfig

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+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_MAIN_STACK_SIZE=2048
+CONFIG_CLOCK_CONTROL=y