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Add support for more Intel registers #2014

Merged
merged 5 commits into from
Sep 29, 2024
Merged

Add support for more Intel registers #2014

merged 5 commits into from
Sep 29, 2024

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elicn
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@elicn elicn commented Sep 28, 2024 •
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Highlights:

  • Added read and write support for CR8, though changes to this reg have no effect currently
  • Fixed a bug in which CR3 got updated whenever CR1 and CR2 were written
  • Initial support for AVX512
    • Added read and write support for XMM8-15 (all modes) and XMM16-31 (64-bit mode)
    • Added read and write support for YMM8-15 (all modes) and YMM16-31 (64-bit mode)
    • Added read and write support for ZMM0-31 (64-bit mode)
    • Writes to XMMn were tested to be reflected in YMMn and ZMMn and vice versa

@elicn elicn marked this pull request as draft September 28, 2024 21:17
@elicn elicn marked this pull request as ready for review September 28, 2024 21:49
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wtdcode commented Sep 29, 2024

LGTM.

@wtdcode wtdcode merged commit 35a6b14 into unicorn-engine:dev Sep 29, 2024
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@elicn elicn deleted the more-x86-regs branch September 29, 2024 09:25
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@elicn @wtdcode