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rv64 compatibility update
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@ua1arn
ua1arn committed Mar 29, 2024
1 parent 89e68c7 commit fd087b2
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Showing 2 changed files with 26 additions and 26 deletions.
18 changes: 9 additions & 9 deletions src/common/tusb_common.h
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Original file line number Diff line number Diff line change
Expand Up @@ -159,15 +159,15 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align(uint32_t value, uint32_t a
return value & ((uint32_t) ~(alignment-1));
}

TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align4 (uint32_t value) { return (value & 0xFFFFFFFCUL); }
TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align8 (uint32_t value) { return (value & 0xFFFFFFF8UL); }
TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align16 (uint32_t value) { return (value & 0xFFFFFFF0UL); }
TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align32 (uint32_t value) { return (value & 0xFFFFFFE0UL); }
TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align4k (uint32_t value) { return (value & 0xFFFFF000UL); }
TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_offset4k(uint32_t value) { return (value & 0xFFFUL); }

TU_ATTR_ALWAYS_INLINE static inline bool tu_is_aligned32(uint32_t value) { return (value & 0x1FUL) == 0; }
TU_ATTR_ALWAYS_INLINE static inline bool tu_is_aligned64(uint64_t value) { return (value & 0x3FUL) == 0; }
TU_ATTR_ALWAYS_INLINE static inline uintptr_t tu_align4 (uintptr_t value) { return value & ~ (uintptr_t) 0x003; }
TU_ATTR_ALWAYS_INLINE static inline uintptr_t tu_align8 (uintptr_t value) { return value & ~ (uintptr_t) 0x007; }
TU_ATTR_ALWAYS_INLINE static inline uintptr_t tu_align16 (uintptr_t value) { return value & ~ (uintptr_t) 0x00F; }
TU_ATTR_ALWAYS_INLINE static inline uintptr_t tu_align32 (uintptr_t value) { return value & ~ (uintptr_t) 0x001F; }
TU_ATTR_ALWAYS_INLINE static inline uintptr_t tu_align4k (uintptr_t value) { return value & ~ (uintptr_t) 0xFFFF; }
TU_ATTR_ALWAYS_INLINE static inline uintptr_t tu_offset4k(uintptr_t value) { return (value & 0xFFF); }

TU_ATTR_ALWAYS_INLINE static inline bool tu_is_aligned32(uintptr_t value) { return (value & 0x1FUL) == 0; }
TU_ATTR_ALWAYS_INLINE static inline bool tu_is_aligned64(uintptr_t value) { return (value & 0x3FUL) == 0; }

//------------- Mathematics -------------//
TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_div_ceil(uint32_t v, uint32_t d) { return (v + d -1)/d; }
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34 changes: 17 additions & 17 deletions src/portable/ohci/ohci.c
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Original file line number Diff line number Diff line change
Expand Up @@ -196,7 +196,7 @@ bool hcd_init(uint8_t rhport)
tu_memclr(&ohci_data, sizeof(ohci_data_t));
for(uint8_t i=0; i<32; i++)
{ // assign all interrupt pointers to period head ed
ohci_data.hcca.interrupt_table[i] = (uint32_t) _phys_addr(&ohci_data.period_head_ed);
ohci_data.hcca.interrupt_table[i] = (uintptr_t) _phys_addr(&ohci_data.period_head_ed);
}

ohci_data.control[0].ed.skip = 1;
Expand Down Expand Up @@ -230,9 +230,9 @@ bool hcd_init(uint8_t rhport)
while( OHCI_REG->command_status_bit.controller_reset ) {} // should not take longer than 10 us

//------------- init ohci registers -------------//
OHCI_REG->control_head_ed = (uint32_t) _phys_addr(&ohci_data.control[0].ed);
OHCI_REG->bulk_head_ed = (uint32_t) _phys_addr(&ohci_data.bulk_head_ed);
OHCI_REG->hcca = (uint32_t) _phys_addr(&ohci_data.hcca);
OHCI_REG->control_head_ed = (uintptr_t) _phys_addr(&ohci_data.control[0].ed);
OHCI_REG->bulk_head_ed = (uintptr_t) _phys_addr(&ohci_data.bulk_head_ed);
OHCI_REG->hcca = (uintptr_t) _phys_addr(&ohci_data.hcca);

OHCI_REG->interrupt_disable = OHCI_REG->interrupt_enable; // disable all interrupts
OHCI_REG->interrupt_status = OHCI_REG->interrupt_status; // clear current set bits
Expand Down Expand Up @@ -407,7 +407,7 @@ static ohci_ed_t * ed_find_free(void)
static void ed_list_insert(ohci_ed_t * p_pre, ohci_ed_t * p_ed)
{
p_ed->next = p_pre->next;
p_pre->next = (uint32_t) _phys_addr(p_ed);
p_pre->next = (uintptr_t) _phys_addr(p_ed);
}

static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr)
Expand All @@ -416,7 +416,7 @@ static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr)

while( p_prev->next )
{
ohci_ed_t* ed = (ohci_ed_t*) _virt_addr((void *)p_prev->next);
ohci_ed_t* ed = (ohci_ed_t*) _virt_addr((void *) (uintptr_t) p_prev->next);

if (ed->dev_addr == dev_addr)
{
Expand All @@ -427,12 +427,12 @@ static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr)
p_prev->next = ed->next;

// point the removed ED's next pointer to list head to make sure HC can always safely move away from this ED
ed->next = (uint32_t) _phys_addr(p_head);
ed->next = (uintptr_t) _phys_addr(p_head);
ed->used = 0;
ed->skip = 0;
}else
{
p_prev = (ohci_ed_t*) _virt_addr((void *)p_prev->next);
p_prev = (ohci_ed_t*) _virt_addr((void *) (uintptr_t) p_prev->next);
}
}
}
Expand All @@ -452,11 +452,11 @@ static void td_insert_to_ed(ohci_ed_t* p_ed, ohci_gtd_t * p_gtd)
// tail is always NULL
if ( tu_align16(p_ed->td_head.address) == 0 )
{ // TD queue is empty --> head = TD
p_ed->td_head.address |= (uint32_t) _phys_addr(p_gtd);
p_ed->td_head.address |= (uintptr_t) _phys_addr(p_gtd);
}
else
{ // TODO currently only support queue up to 2 TD each endpoint at a time
((ohci_gtd_t*) tu_align16((uint32_t)_virt_addr((void *)p_ed->td_head.address)))->next = (uint32_t) _phys_addr(p_gtd);
((ohci_gtd_t*) tu_align16((uintptr_t)_virt_addr((void *) (uintptr_t) p_ed->td_head.address)))->next = (uintptr_t) _phys_addr(p_gtd);
}
ohci_data_clean_invalidate();
}
Expand Down Expand Up @@ -516,7 +516,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
qtd->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;

//------------- Attach TDs list to Control Endpoint -------------//
ed->td_head.address = (uint32_t) _phys_addr(qtd);
ed->td_head.address = (uintptr_t) _phys_addr(qtd);

ohci_data_clean_invalidate();
OHCI_REG->command_status_bit.control_list_filled = 1;
Expand Down Expand Up @@ -548,7 +548,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
gtd->data_toggle = GTD_DT_DATA1; // Both Data and Ack stage start with DATA1
gtd->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;

ed->td_head.address = (uint32_t) _phys_addr(gtd);
ed->td_head.address = (uintptr_t) _phys_addr(gtd);

ohci_data_clean_invalidate();
OHCI_REG->command_status_bit.control_list_filled = 1;
Expand Down Expand Up @@ -609,10 +609,10 @@ static ohci_td_item_t* list_reverse(ohci_td_item_t* td_head)
while(td_head != NULL)
{
td_head = _virt_addr(td_head);
uint32_t next = td_head->next;
uintptr_t next = td_head->next;

// make current's item become reverse's first item
td_head->next = (uint32_t) td_reverse_head;
td_head->next = (uintptr_t) td_reverse_head;
td_reverse_head = _phys_addr(td_head);

td_head = (ohci_td_item_t*) next; // advance to next item
Expand All @@ -623,7 +623,7 @@ static ohci_td_item_t* list_reverse(ohci_td_item_t* td_head)

static inline bool gtd_is_control(ohci_gtd_t const * const p_qtd)
{
return ((uint32_t) p_qtd) < ((uint32_t) ohci_data.gtd_pool); // check ohci_data_t for memory layout
return ((uintptr_t) p_qtd) < ((uintptr_t) ohci_data.gtd_pool); // check ohci_data_t for memory layout
}

static inline ohci_ed_t* gtd_get_ed(ohci_gtd_t const * const p_qtd)
Expand Down Expand Up @@ -653,7 +653,7 @@ static void done_queue_isr(uint8_t hostid)
(void) hostid;

// done head is written in reversed order of completion --> need to reverse the done queue first
ohci_td_item_t* td_head = list_reverse ( (ohci_td_item_t*) tu_align16(ohci_data.hcca.done_head) );
ohci_td_item_t* td_head = list_reverse ( (ohci_td_item_t*) tu_align16((uintptr_t) ohci_data.hcca.done_head) );
ohci_data.hcca.done_head = 0;

while( td_head != NULL )
Expand Down Expand Up @@ -690,7 +690,7 @@ static void done_queue_isr(uint8_t hostid)
hcd_event_xfer_complete(ed->dev_addr, tu_edpt_addr(ed->ep_number, dir), xferred_bytes, event, true);
}

td_head = (ohci_td_item_t*) _virt_addr((void *)td_head->next);
td_head = (ohci_td_item_t*) _virt_addr((void *) (uintptr_t) td_head->next);
}
ohci_data_clean_invalidate();
}
Expand Down

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