Handle TU_BREAKPOINT

ua1arn · Sep 10, 2024 · 33a3da5 · 33a3da5
1 parent c0b8219
commit 33a3da5
Showing 1 changed file with 3 additions and 1 deletion.
diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h
@@ -76,7 +76,9 @@
 #endif
 
 // Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7, M33. M55
-#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) || \
+#if 1
+	#define TU_BREAKPOINT() do { ASSERT(0); } while(0)
+#elif defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) || \
     defined(__ARM7M__) || defined (__ARM7EM__) || defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
   #define TU_BREAKPOINT() do {                                                                              \
     volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \