一款专门用于5G基带芯片加速器调度的RISC-V MCU，满足快速响应的需求并且能够自主可控
- 对Scala和Chisel进行学习，使用Chisel完成一个简单的CPU，项目地址
- 参考开源项目，如果壳、蜂鸟
- 设计Fast Interrupt CPU，代码仓库
- 实现Fast Interrupt CPU并且验证, doing
- 接入到基带芯片中完成测试
- 支持RV32-IMC指令集
- 支持Difftest测试
- 支持中断嵌套、中断尾链
- 采用ITCM、DTCM，可配置I-Cache
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- Verilog 55.8%
- Assembly 26.5%
- Jupyter Notebook 6.2%
- Scala 5.9%
- C 2.0%
- Makefile 1.4%
- Other 2.2%