✨ add optional CPU clock gating #775
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clk_i: main clock, can be switched off clk_aux_i: always-on clock
- SYSINFO->SOC bit 7 - some minor VHDL clean-ups (remove use of custom bool-to-std_ulogic function)
- minor code clean-ups (remove private print true/false function)
default = false; update version ID
- add new CLOCK_GATING_EN generic
- simplify instruction fetch engine: remove PARKED state, use the IPB FIFO level to check if the instruction fetch has halted - make sure halt request signal is not registered by the switched-off clock - add registered sleep mode signal
- add CPU's clk_aux_i port - add new processor generic CLOCK_GATING_EN - refine section "sleep mode"
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This PR adds an optional clock gating mechanism to the processor. When enabled, the clock of the CPU core is shut down during sleep mode to reduce power consumption. This concept was developed/proposed by @mikaelsky in #772.
neorv32_clockgate.vhdthat implements the clock switchA secondary, always-on clock is added to the CPU. This additional clock is used to keep the interrupt buffer logic active while the rest of the CPU is switched off. Any (enabled) interrupt request (including a debug halt request) will make the CPU leave sleep mode.
The CPU's sleep signal is set high only when
Right now, just the CPU core is turned off during sleep mode. But I think it might be possible to shut down the caches and bus switch as well. If the DMA is not required the entire interconnect could be shut down as well.