minor rtl cleanups and optimization

CHANGELOG.md

@@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date | Version | Comment | Ticket |
 |:----:|:-------:|:--------|:------:|
+| 21.12.2024 | 1.10.7.6 | minor rtl cleanups and optimizations | [#1123](https://github.com/stnolting/neorv32/pull/1123) |
 | 19.12.2024 | 1.10.7.5 | :test_tube: use time-multiplex PMP architecture (reducing area footprint) | [#1105](https://github.com/stnolting/neorv32/pull/1105) |
 | 14.12.2024 | 1.10.7.4 | :sparkles: add new module: I2C-compatible **Two-Wire Device Controller (TWD)** | [#1121](https://github.com/stnolting/neorv32/pull/1121) |
 | 14.12.2024 | 1.10.7.3 | :warning: rework TRNG (change HAL; remove interrupt) | [#1120](https://github.com/stnolting/neorv32/pull/1120) |

docs/datasheet/overview.adoc

@@ -282,11 +282,6 @@ puts "NEORV32 source files:"
 puts $file_list
 ----
 
-.File-List Usage Examples
-[TIP]
-The provided file-list files are used by the GHDL-based simple simulation setup (`sim/ghdl.setup.sh`) as
-well as by the Vivado IP packager script (`rtl/system_integration/neorv32_vivado_ip.tcl`).
-
 
 <<<
 // ####################################################################################################################

rtl/core/neorv32_bus.vhd

@@ -374,7 +374,9 @@ use neorv32.neorv32_package.all;
 
 entity neorv32_bus_io_switch is
   generic (
-    DEV_SIZE  : natural; -- size of each single IO device, has to be a power of two
+    INREG_EN  : boolean := false; -- enable main_req_i register stage
+    OUTREG_EN : boolean := false; -- enable main_rsp_o register stage
+    DEV_SIZE  : natural := 256; -- size of each single IO device, has to be a power of two
     -- device port enable and base address; enabled ports do not have to be contiguous --
     DEV_00_EN : boolean := false; DEV_00_BASE : std_ulogic_vector(31 downto 0) := (others => '0');
     DEV_01_EN : boolean := false; DEV_01_BASE : std_ulogic_vector(31 downto 0) := (others => '0');
@@ -485,8 +487,9 @@ architecture neorv32_bus_io_switch_rtl of neorv32_bus_io_switch is
   signal dev_req : dev_req_t;
   signal dev_rsp : dev_rsp_t;
 
-  -- (partial) register stage --
+  -- register stages --
   signal main_req : bus_req_t;
+  signal main_rsp : bus_rsp_t;
 
 begin
 
@@ -526,29 +529,27 @@ begin
   dev_31_req_o <= dev_req(31); dev_rsp(31) <= dev_31_rsp_i;
 
 
-  -- Input Buffer ---------------------------------------------------------------------------
+  -- Optional Input Register ----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  request_reg: process(rstn_i, clk_i)
-  begin
-    if (rstn_i = '0') then
-      main_req.addr <= (others => '0');
-      main_req.stb  <= '0';
-    elsif rising_edge(clk_i) then
-      if (main_req_i.stb = '1') then -- reduce switching activity on IO bus system
-        main_req.addr <= main_req_i.addr;
+  input_reg_enabled:
+  if INREG_EN generate
+    request_reg: process(rstn_i, clk_i)
+    begin
+      if (rstn_i = '0') then
+        main_req <= req_terminate_c;
+      elsif rising_edge(clk_i) then
+        if (main_req_i.stb = '1') then -- reduce switching activity on IO bus system
+          main_req <= main_req_i;
+        end if;
+        main_req.stb <= main_req_i.stb;
       end if;
-      main_req.stb <= main_req_i.stb;
-    end if;
-  end process request_reg;
+    end process request_reg;
+  end generate;
 
-  -- no need to register these signals; they are stable for the entire transfer and do not impact the critical path --
-  main_req.data  <= main_req_i.data;
-  main_req.ben   <= main_req_i.ben;
-  main_req.rw    <= main_req_i.rw;
-  main_req.src   <= main_req_i.src;
-  main_req.priv  <= main_req_i.priv;
-  main_req.rvso  <= main_req_i.rvso;
-  main_req.fence <= main_req_i.fence;
+  input_reg_disabled:
+  if not INREG_EN generate
+    main_req <= main_req_i;
+  end generate;
 
 
   -- Request --------------------------------------------------------------------------------
@@ -590,10 +591,30 @@ begin
         tmp_v.err  := tmp_v.err  or dev_rsp(i).err;
       end if;
     end loop;
-    main_rsp_o <= tmp_v;
+    main_rsp <= tmp_v;
   end process;
 
 
+  -- Optional Output Register ---------------------------------------------------------------
+  -- -------------------------------------------------------------------------------------------
+  output_reg_enabled:
+  if OUTREG_EN generate
+    response_reg: process(rstn_i, clk_i)
+    begin
+      if (rstn_i = '0') then
+        main_rsp_o <= rsp_terminate_c;
+      elsif rising_edge(clk_i) then
+        main_rsp_o <= main_rsp;
+      end if;
+    end process response_reg;
+  end generate;
+
+  output_reg_disabled:
+  if not OUTREG_EN generate
+    main_rsp_o <= main_rsp;
+  end generate;
+
+
 end neorv32_bus_io_switch_rtl;
 
 

rtl/core/neorv32_cache.vhd

@@ -40,8 +40,8 @@ use neorv32.neorv32_package.all;
 
 entity neorv32_cache is
   generic (
-    NUM_BLOCKS : natural range 2 to 4096;       -- number of cache blocks (min 2), has to be a power of 2
-    BLOCK_SIZE : natural range 4 to 4096;       -- cache block size in bytes (min 4), has to be a power of 2
+    NUM_BLOCKS : natural range 2 to 1024;       -- number of cache blocks (min 2), has to be a power of 2
+    BLOCK_SIZE : natural range 4 to 32768;      -- cache block size in bytes (min 4), has to be a power of 2
     UC_BEGIN   : std_ulogic_vector(3 downto 0); -- begin of uncached address space (page number / 4 MSBs of address)
     UC_ENABLE  : boolean;                       -- enable direct/uncached accesses
     READ_ONLY  : boolean                        -- read-only accesses for host