[docs] IO: remove access restrictions

stnolting · Jan 7, 2025 · 59decee · 59decee
1 parent 0deb073
commit 59decee
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Showing 26 changed files with 1 addition and 27 deletions.
diff --git a/docs/datasheet/soc_bootrom.adoc b/docs/datasheet/soc_bootrom.adoc
@@ -11,7 +11,6 @@
 | Top entity ports:       | none                         |
 | Configuration generics: | `BOOT_MODE_SELECT`           | implement BOOTROM when `BOOT_MODE_SELECT` = 0; see <<_boot_configuration>>
 | CPU interrupts:         | none                         |
-| Access restrictions:  2+| read-only
 |=======================
 
 
@@ -20,6 +19,7 @@
 The boot ROM contains the executable image of the default NEORV32 <<_bootloader>>. When the
 <<_boot_configuration>> is set to _bootloader_ mode (0) via the `BOOT_MODE_SELECT` generic, the
 boot ROM is automatically enabled and the CPU boot address is adjusted to the base address of the boot ROM.
+Note that the entire boot ROM is read-only.
 
 .Bootloader Image
 [IMPORTANT]

diff --git a/docs/datasheet/soc_cfs.adoc b/docs/datasheet/soc_cfs.adoc
@@ -15,7 +15,6 @@
 |                         | `IO_CFS_IN_SIZE`   | size of `cfs_in_i`
 |                         | `IO_CFS_OUT_SIZE`  | size of `cfs_out_o`
 | CPU interrupts:         | fast IRQ channel 1 | CFS interrupt (see <<_processor_interrupts>>)
-| Access restrictions:  2+| non-32-bit write accesses are ignored
 |=======================
 
 

diff --git a/docs/datasheet/soc_clint.adoc b/docs/datasheet/soc_clint.adoc
@@ -14,7 +14,6 @@
 | Configuration generics: | `IO_CLINT_EN`     | implement core local interruptor when `true`
 | CPU interrupts:         | `MTI`             | machine timer interrupt (see <<_processor_interrupts>>)
 |                         | `MSI`             | machine software interrupt (see <<_processor_interrupts>>)
-| Access restrictions:  2+| non-32-bit write accesses are ignored
 |=======================
 
 

diff --git a/docs/datasheet/soc_crc.adoc b/docs/datasheet/soc_crc.adoc
@@ -11,7 +11,6 @@
 | Top entity ports:       | none |
 | Configuration generics: | `IO_CRC_EN` | implement CRC module when `true`
 | CPU interrupts:         | none |
-| Access restrictions:  2+| non-32-bit write accesses are ignored
 |=======================
 
 

diff --git a/docs/datasheet/soc_dcache.adoc b/docs/datasheet/soc_dcache.adoc
@@ -12,7 +12,6 @@
 |                         | `DCACHE_NUM_BLOCKS` | number of cache blocks (pages/lines)
 |                         | `DCACHE_BLOCK_SIZE` | size of a cache block in bytes
 | CPU interrupts:         | none |
-| Access restrictions:  2+| none
 |=======================
 
 

diff --git a/docs/datasheet/soc_dma.adoc b/docs/datasheet/soc_dma.adoc
@@ -11,7 +11,6 @@
 | Top entity ports:       | none |
 | Configuration generics: | `IO_DMA_EN` | implement DMA when `true`
 | CPU interrupts:         | fast IRQ channel 10 | DMA transfer done (see <<_processor_interrupts>>)
-| Access restrictions:  2+| non-32-bit write accesses are ignored
 |=======================
 
 

diff --git a/docs/datasheet/soc_dmem.adoc b/docs/datasheet/soc_dmem.adoc
@@ -11,7 +11,6 @@
 | Configuration generics: | `MEM_INT_DMEM_EN`   | implement processor-internal DMEM when `true`
 |                         | `MEM_INT_DMEM_SIZE` | DMEM size in bytes (use a power of 2)
 | CPU interrupts:         | none                |
-| Access restrictions:  2+| none
 |=======================
 
 

diff --git a/docs/datasheet/soc_gpio.adoc b/docs/datasheet/soc_gpio.adoc
@@ -12,7 +12,6 @@
 |                         | `gpio_i` | 64-bit parallel input port
 | Configuration generics: | `IO_GPIO_NUM` | number of input/output pairs to implement (0..64)
 | CPU interrupts:         | none |
-| Access restrictions:  2+| non-32-bit write accesses are ignored
 |=======================
 
 

diff --git a/docs/datasheet/soc_gptmr.adoc b/docs/datasheet/soc_gptmr.adoc
@@ -11,7 +11,6 @@
 | Top entity ports:       | none |
 | Configuration generics: | `IO_GPTMR_EN` | implement general purpose timer when `true`
 | CPU interrupts:         | fast IRQ channel 12 | timer interrupt (see <<_processor_interrupts>>)
-| Access restrictions:  2+| non-32-bit write accesses are ignored
 |=======================
 
 

diff --git a/docs/datasheet/soc_icache.adoc b/docs/datasheet/soc_icache.adoc
@@ -12,7 +12,6 @@
 |                         | `ICACHE_NUM_BLOCKS` | number of cache blocks (pages/lines)
 |                         | `ICACHE_BLOCK_SIZE` | size of a cache block in bytes
 | CPU interrupts:         | none |
-| Access restrictions:  2+| none
 |=======================
 
 

diff --git a/docs/datasheet/soc_imem.adoc b/docs/datasheet/soc_imem.adoc
@@ -13,7 +13,6 @@
 |                         | `MEM_INT_IMEM_SIZE`           | IMEM size in bytes (use a power of 2)
 |                         | `BOOT_MODE_SELECT`            | implement IMEM as ROM when `BOOT_MODE_SELECT` = 2; see <<_boot_configuration>>
 | CPU interrupts:         | none                          |
-| Access restrictions:  2+| none / read-only if `INT_BOOTLOADER_EN = true`
 |=======================
 
 

diff --git a/docs/datasheet/soc_neoled.adoc b/docs/datasheet/soc_neoled.adoc
@@ -12,7 +12,6 @@
 | Configuration generics: | `IO_NEOLED_EN`      | implement NEOLED controller when `true`
 |                         | `IO_NEOLED_TX_FIFO` | TX FIFO depth, has to be a power of 2, min 1
 | CPU interrupts:         | fast IRQ channel 9  | configurable NEOLED data FIFO interrupt (see <<_processor_interrupts>>)
-| Access restrictions:  2+| non-32-bit write accesses are ignored
 |=======================
 
 

diff --git a/docs/datasheet/soc_onewire.adoc b/docs/datasheet/soc_onewire.adoc
@@ -13,7 +13,6 @@
 | Configuration generics: | `IO_ONEWIRE_EN`     | implement ONEWIRE interface controller when `true`
 |                         | `IO_ONEWIRE_FIFO`   | RTX fifo depth, has to be zero or a power of two, min 1
 | CPU interrupts:         | fast IRQ channel 13 | operation done interrupt (see <<_processor_interrupts>>)
-| Access restrictions:  2+| non-32-bit write accesses are ignored
 |=======================
 
 

diff --git a/docs/datasheet/soc_pwm.adoc b/docs/datasheet/soc_pwm.adoc
@@ -11,7 +11,6 @@
 | Top entity ports:       | `pwm_o` | PWM output channels (16-bit)
 | Configuration generics: | `IO_PWM_NUM_CH` | number of PWM channels to implement (0..16)
 | CPU interrupts:         | none |
-| Access restrictions:  2+| non-32-bit write accesses are ignored
 |=======================
 
 

diff --git a/docs/datasheet/soc_sdi.adoc b/docs/datasheet/soc_sdi.adoc
@@ -15,7 +15,6 @@
 | Configuration generics: | `IO_SDI_EN`   | implement SDI controller when `true`
 |                         | `IO_SDI_FIFO` | data FIFO size, has to a power of two, min 1
 | CPU interrupts:         | fast IRQ channel 11 | configurable SDI interrupt (see <<_processor_interrupts>>)
-| Access restrictions:  2+| non-32-bit write accesses are ignored
 |=======================
 
 

diff --git a/docs/datasheet/soc_slink.adoc b/docs/datasheet/soc_slink.adoc
@@ -23,7 +23,6 @@
 |                         | `IO_SLINK_TX_FIFO`  | TX FIFO depth (1..32k), has to be a power of two, min 1
 | CPU interrupts:         | fast IRQ channel 14 | RX SLINK IRQ (see <<_processor_interrupts>>)
 |                         | fast IRQ channel 15 | TX SLINK IRQ (see <<_processor_interrupts>>)
-| Access restrictions:  2+| non-32-bit write accesses are ignored
 |=======================
 
 

diff --git a/docs/datasheet/soc_spi.adoc b/docs/datasheet/soc_spi.adoc
@@ -15,7 +15,6 @@
 | Configuration generics: | `IO_SPI_EN`   | implement SPI controller when `true`
 |                         | `IO_SPI_FIFO` | FIFO depth, has to be a power of two, min 1
 | CPU interrupts:         | fast IRQ channel 6 | configurable SPI interrupt (see <<_processor_interrupts>>)
-| Access restrictions:  2+| non-32-bit write accesses are ignored
 |=======================
 
 

diff --git a/docs/datasheet/soc_sysinfo.adoc b/docs/datasheet/soc_sysinfo.adoc
@@ -10,7 +10,6 @@
 | Top entity ports:       | none |
 | Configuration generics: | * | most of the top's configuration generics
 | CPU interrupts:         | none |
-| Access restrictions:  2+| non-32-bit write accesses are ignored
 |=======================
 
 

diff --git a/docs/datasheet/soc_trng.adoc b/docs/datasheet/soc_trng.adoc
@@ -12,7 +12,6 @@
 | Configuration generics: | `IO_TRNG_EN`   | implement TRNG when `true`
 |                         | `IO_TRNG_FIFO` | data FIFO depth, min 1, has to be a power of two
 | CPU interrupts:         | none
-| Access restrictions:  2+| non-32-bit write accesses are ignored
 |=======================
 
 

diff --git a/docs/datasheet/soc_twd.adoc b/docs/datasheet/soc_twd.adoc
@@ -15,7 +15,6 @@
 | Configuration generics: | `IO_TWD_EN`        | implement TWD controller when `true`
 |                         | `IO_TWD_FIFO`      | RX/TX FIFO depth, has to be a power of two, min 1
 | CPU interrupts:         | fast IRQ channel 0 | FIFO status interrupt (see <<_processor_interrupts>>)
-| Access restrictions:  2+| non-32-bit write accesses are ignored
 |=======================
 
 

diff --git a/docs/datasheet/soc_twi.adoc b/docs/datasheet/soc_twi.adoc
@@ -15,7 +15,6 @@
 | Configuration generics: | `IO_TWI_EN`        | implement TWI controller when `true`
 |                         | `IO_TWI_FIFO`      | FIFO depth, has to be a power of two, min 1
 | CPU interrupts:         | fast IRQ channel 7 | FIFO empty and module idle interrupt (see <<_processor_interrupts>>)
-| Access restrictions:  2+| non-32-bit write accesses are ignored
 |=======================
 
 

diff --git a/docs/datasheet/soc_uart.adoc b/docs/datasheet/soc_uart.adoc
@@ -17,7 +17,6 @@
 |                         | `UART0_TX_FIFO` | TX FIFO depth (power of 2, min 1)
 | CPU interrupts:         | fast IRQ channel 2 | RX interrupt
 |                         | fast IRQ channel 3 | TX interrupt (see <<_processor_interrupts>>)
-| Access restrictions:  2+| non-32-bit write accesses are ignored
 |=======================
 
 

diff --git a/docs/datasheet/soc_wdt.adoc b/docs/datasheet/soc_wdt.adoc
@@ -11,7 +11,6 @@
 | Top entity ports:       | none |
 | Configuration generics: | `IO_WDT_EN` | implement watchdog when `true`
 | CPU interrupts:         | none |
-| Access restrictions:  2+| non-32-bit write accesses are ignored
 |=======================
 
 

diff --git a/docs/datasheet/soc_xbus.adoc b/docs/datasheet/soc_xbus.adoc
@@ -25,7 +25,6 @@
 |                         | `XBUS_CACHE_NUM_BLOCKS` | number of blocks ("lines"), has to be a power of two.
 |                         | `XBUS_CACHE_BLOCK_SIZE` | size in bytes of each block, has to be a power of two.
 | CPU interrupts:         | none |
-| Access restrictions:  2+| none
 |=======================
 
 

diff --git a/docs/datasheet/soc_xip.adoc b/docs/datasheet/soc_xip.adoc
@@ -18,8 +18,6 @@
 |                         | `XIP_CACHE_NUM_BLOCKS` | number of blocks in XIP cache; has to be a power of two
 |                         | `XIP_CACHE_BLOCK_SIZE` | number of bytes per XIP cache block; has to be a power of two, min 4
 | CPU interrupts:         | none                   |
-| Access restrictions:  2+| control registers: non-32-bit write accesses are ignored
-|                       2+| XIP data access: read-only
 |=======================
 
 

diff --git a/docs/datasheet/soc_xirq.adoc b/docs/datasheet/soc_xirq.adoc
@@ -11,7 +11,6 @@
 | Top entity ports:       | `xirq_i`           | External interrupts input (32-bit)
 | Configuration generics: | `XIRQ_NUM_CH`      | Number of external IRQ channels to implement (0..32)
 | CPU interrupts:         | fast IRQ channel 8 | XIRQ (see <<_processor_interrupts>>)
-| Access restrictions:  2+| non-32-bit write accesses are ignored
 |=======================