[cpu] bus fence comment edit

stnolting · Feb 11, 2024 · 5235d6e · 5235d6e
1 parent 14778bb
commit 5235d6e
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Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/rtl/core/neorv32_cpu_control.vhd b/rtl/core/neorv32_cpu_control.vhd
@@ -438,7 +438,7 @@ begin
   bus_req_o.rw    <= '0'; -- read-only
   bus_req_o.src   <= '1'; -- source = instruction fetch
   bus_req_o.rvso  <= '0'; -- cannot be a reservation set operation
-  bus_req_o.fence <= ctrl.lsu_fence; -- fence(.i) operation
+  bus_req_o.fence <= ctrl.lsu_fence; -- fence(.i) operation, valid without STB being set
 
 
   -- Instruction Prefetch Buffer (FIFO) -----------------------------------------------------

diff --git a/rtl/core/neorv32_cpu_lsu.vhd b/rtl/core/neorv32_cpu_lsu.vhd
@@ -125,7 +125,7 @@ begin
   bus_req_o.src <= '0'; -- 0 = data access
 
   -- data/instruction fence(.i)
-  bus_req_o.fence <= ctrl_i.lsu_fence;
+  bus_req_o.fence <= ctrl_i.lsu_fence; -- this is valid even without STB being set
 
 
   -- Data Output - Alignment and Byte Enable ------------------------------------------------