This repository is a port of the "RISCOF RISC-V Architectural Test Framework" to test the NEORV32 RISC-V Processor for compatibility to the RISC-V user and privileged ISA specifications. Sail RISC-V is used as reference model. Currently, the following tests are supported:
-
rv32i_m\B
- bit-manipulation (Zba
+Zbb
+Zbs
) -
rv32i_m\C
- compressed instructions -
rv32i_m\I
- base integer ISA -
rv32i_m\K
- scalar cryptography,Zkn
andZks
(Zbkb
+Zbkc
+Zbkx
+Zknd
+Zkne
+Zknh
+Zksed
+Zksh
) -
rv32i_m\M
- hardware integer multiplication and division -
rv32i_m\privilege
- privileged machine-mode architecture -
rv32i_m\Zicond
- conditional operations -
rv32i_m\Zifencei
- instruction stream synchronization
Tip
The general structure of this repository was setup according to the RISCOF installation guide.
Several tools and submodules are required to run this port of the architecture test framework. The repository's GitHub Actions workflow takes care of installing all the required packages.
- neorv32 submodule - the device under test (DUT)
- riscv-arch-test submodule - architecture test cases
- RISC-V GCC toolchain - for compiling native
rv32
code - Sail RISC-V - the reference model (a pre-built binary can be found in
the
bin
folder) - RISCOF - the architecture test framework (including riscv-isac and riscv-config)
- GHDL - the awesome VHDL simulator for simulating the DUT
The framework (running all tests) is invoked via a single shell script
run.sh
that returns 0 if all tests were executed
successfully or 1 if there were any errors. The exit code of this script is used to determine the overall success
of the GitHub Actions workflow.
The RISCOF config.ini file is used to configure
the plugins to be used: the device-under-test ("DUT") and the reference model ("REF"). The ISA, debug and platform
specifications, which define target-specific configurations like available ISA extensions, ISA spec. versions and
platform modules (like MTIME), are defined by YAML
files in the according plugin folders.
- DUT:
neorv32
inplugin-neorv32
- REF:
sail_cSim
inplugin-sail_cSim
Each plugin folder also provides low-level environment files like linker scripts (to generate an executable image matching the target's memory layout) as well as platform-specific code (for example to initialize the target and to dump the final test signatures/results).
The official RISC-V architecture tests repository provides the individual test cases for all (ratified) RISC-V ISA extensions (user and privilege ISA) that are currently supported by the DUT. Each test case checks a single instruction or core feature and is compiled into a plugin-specific executable using a prebuilt RISC-V GCC toolchain.
The "golden reference" data is generated by the Sail RISC-V Model. This data is compared against the results of the DUT. The final test report is made available as CSS-flavored HTML file via the GitHib actions artifact.
Tip
Prebuilt sail-riscv binaries for 64-bit x86 Linux are available in the
bin
folder.
The sim
folder provides a plain-VHDL testbench
and shell scripts to simulate the NEORV32 processor using GHDL. The testbench provides generics to configure the
DUT's RISC-V ISA extensions and also to pass a plain ASCII HEX file, which represents the memory image containing
the actual executable. This file generated from a test-case-specific ELF file. The makefile in the sim
folder
takes care of compilation and will also convert the final memory image into a plain HEX file. Note that this makefile
uses the default software framework from the NEORV32 submodule.
The testbench implements a CPU-external memory module that get initialized with the actual memory image generated by the
test framework. This memory is attached to the processor via its external Wishbone bus interface and is mapped to the core's
reset address at 0x00000000
. The memory is implemented as 4 individual byte-wide memories each providing 1/4 of the total
memory size. This "splitting" is required as GHDL has problems handling large objects (see ghdl/ghdl#1592).
The final test result data (= test signature) is written to a file (DUT-neorv32.signature
) by the testbench via
consecutive write accesses to address 0xF0000004
. The testbench also provides several memory-mapped "triggers" (at
address 0xF0000000
) to quit the current simulation using VHDL08's finish
statement or to trigger CPU-external
RISC-V machine-level interrupts (MTI: machine timer interrupt; MEI: machine external interrupt; MSI: machine software
interrupt).
The simulation scripts and the makefile for generating the memory initialization file are invoked and orchestrated from
a DUT-specific Python script in the DUT's plugin folder
(-> plugin-neorv32/riscof_neorv32.py
).
This Python script makes extensive use of shell commands to move and execute files and scripts.
Important
The Python scripts of both plugins override the default SET_REL_TVAL_MSK
macro from
riscv-arch-test/riscv-test-suite/env/arch_test.h
to remove the BREAK exception cause from the relocation list as the
NEORV32 sets mtval
to zero for this type of exception. This is explicitly permitted by the RISC-V priv. spec.