Gpio update

CHANGELOG.md

@@ -32,6 +32,7 @@ This project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Changed
 
+    - `gpio` updates & cleanups: mode after pin numbers (Rust 1.59), default modes
     - Use device-specific features rather than by-peripheral features.
     - Use `fugit` duration nd rate units instead of custom
     - Use const-generics for GPIO (require Rust 1.51)

Cargo.toml

@@ -18,10 +18,11 @@ exclude = [
 	"docs/",
 	"docs/*"
 ]
-edition = "2018"
+edition = "2021"
+rust-version = "1.59"
 
 [dependencies]
-cortex-m = "0.7"
+cortex-m = "0.7.5"
 nb = "0.1.1"
 stm32l4 = "0.14.0"
 embedded-dma = "0.1"
@@ -71,46 +72,54 @@ unproven = ["embedded-hal/unproven"]
 otg_fs = ["synopsys-usb-otg"]
 
 # L4x1
-stm32l431 = [ "stm32l4/stm32l4x1" ]
-stm32l451 = [ "stm32l4/stm32l4x1" ]
-stm32l471 = [ "stm32l4/stm32l4x1" ]
+stm32l431 = [ "stm32l4/stm32l4x1", "gpio-l43x" ]
+stm32l451 = [ "stm32l4/stm32l4x1", "gpio-l45x" ]
+stm32l471 = [ "stm32l4/stm32l4x1", "gpio-l47x" ]
 
 # L412
-stm32l412 = [ "stm32l4/stm32l412" ]
-stm32l422 = [ "stm32l4/stm32l412" ]
+stm32l412 = [ "stm32l4/stm32l412", "gpio-l41x" ]
+stm32l422 = [ "stm32l4/stm32l412", "gpio-l41x" ]
 
 # L4x2
-stm32l432 = [ "stm32l4/stm32l4x2" ]
-stm32l442 = [ "stm32l4/stm32l4x2" ]
-stm32l452 = [ "stm32l4/stm32l4x2" ]
-stm32l462 = [ "stm32l4/stm32l4x2" ]
+stm32l432 = [ "stm32l4/stm32l4x2", "gpio-l43x" ]
+stm32l442 = [ "stm32l4/stm32l4x2", "gpio-l43x" ]
+stm32l452 = [ "stm32l4/stm32l4x2", "gpio-l45x" ]
+stm32l462 = [ "stm32l4/stm32l4x2", "gpio-l45x" ]
 
 # L4x3
-stm32l433 = [ "stm32l4/stm32l4x3" ]
-stm32l443 = [ "stm32l4/stm32l4x3" ]
+stm32l433 = [ "stm32l4/stm32l4x3", "gpio-l43x" ]
+stm32l443 = [ "stm32l4/stm32l4x3", "gpio-l43x" ]
 
 # L4x5
-stm32l475 = [ "stm32l4/stm32l4x5" ]
+stm32l475 = [ "stm32l4/stm32l4x5", "gpio-l47x" ]
 
 # L4x6
-stm32l476 = [ "stm32l4/stm32l4x6" ]
-stm32l486 = [ "stm32l4/stm32l4x6" ]
-stm32l496 = [ "stm32l4/stm32l4x6" ]
-stm32l4a6 = [ "stm32l4/stm32l4x6" ]
+stm32l476 = [ "stm32l4/stm32l4x6", "gpio-l47x" ]
+stm32l486 = [ "stm32l4/stm32l4x6", "gpio-l47x" ]
+stm32l496 = [ "stm32l4/stm32l4x6", "gpio-l49x" ]
+stm32l4a6 = [ "stm32l4/stm32l4x6", "gpio-l49x" ]
 
 # L4+ series PAC support??
-#stm32l4p5 = [ "stm32l4/stm32l4x5" ]
-#stm32l4q5 = [ "stm32l4/stm32l4x5" ]
-#stm32l4r5 = [ "stm32l4/stm32l4x5" ]
-#stm32l4s5 = [ "stm32l4/stm32l4x5" ]
+#stm32l4p5 = [ "stm32l4/stm32l4x5", "gpio-l4p" ]
+#stm32l4q5 = [ "stm32l4/stm32l4x5", "gpio-l4p" ]
+#stm32l4r5 = [ "stm32l4/stm32l4x5", "gpio-l4rx" ]
+#stm32l4s5 = [ "stm32l4/stm32l4x5", "gpio-l4rx" ]
 
 # L4x7
-#stm32l4r7 = [ "stm32l4/stm32l4x7" ]
-#stm32l4s7 = [ "stm32l4/stm32l4x7" ]
+#stm32l4r7 = [ "stm32l4/stm32l4x7", "gpio-l4rx" ]
+#stm32l4s7 = [ "stm32l4/stm32l4x7", "gpio-l4rx" ]
 
 ## L4x9
-stm32l4r9 = [ "stm32l4/stm32l4r9" ] # PAC has an L4r9 specific variation
-stm32l4s9 = [ "stm32l4/stm32l4r9" ]
+stm32l4r9 = [ "stm32l4/stm32l4r9", "gpio-l4rx" ] # PAC has an L4r9 specific variation
+stm32l4s9 = [ "stm32l4/stm32l4r9", "gpio-l4rx" ]
+
+gpio-l41x = []
+gpio-l43x = []
+gpio-l45x = []
+gpio-l47x = []
+gpio-l49x = []
+#gpio-l4p = []
+gpio-l4rx = []
 
 [dev-dependencies]
 panic-halt = "0.2.0"

README.md

@@ -14,7 +14,7 @@ _formerly [MabezDev/stm32l4xx-hal](https://github.com/mabezdev/stm32l4xx-hal)_
 
 ## About
 
-    - Minimum rustc version 1.51
+    - Minimum rustc version 1.59
 
 ## License
 

examples/i2c_write.rs

@@ -37,17 +37,15 @@ fn main() -> ! {
 
     let mut gpioa = dp.GPIOA.split(&mut rcc.ahb2);
 
-    let mut scl =
-        gpioa
-            .pa9
-            .into_alternate_open_drain(&mut gpioa.moder, &mut gpioa.otyper, &mut gpioa.afrh);
-    scl.internal_pull_up(&mut gpioa.pupdr, true);
-
-    let mut sda =
-        gpioa
-            .pa10
-            .into_alternate_open_drain(&mut gpioa.moder, &mut gpioa.otyper, &mut gpioa.afrh);
-    sda.internal_pull_up(&mut gpioa.pupdr, true);
+    let scl = gpioa
+        .pa9
+        .into_alternate_open_drain(&mut gpioa.moder, &mut gpioa.otyper, &mut gpioa.afrh)
+        .internal_pull_up(&mut gpioa.pupdr, true);
+
+    let sda = gpioa
+        .pa10
+        .into_alternate_open_drain(&mut gpioa.moder, &mut gpioa.otyper, &mut gpioa.afrh)
+        .internal_pull_up(&mut gpioa.pupdr, true);
 
     let mut i2c = I2c::i2c1(
         dp.I2C1,

examples/irq_button.rs

@@ -7,7 +7,7 @@ extern crate panic_semihosting;
 extern crate stm32l4xx_hal as hal;
 
 use crate::hal::{
-    gpio::{gpioc::PC13, Edge, ExtiPin, Input, PullUp},
+    gpio::{gpioc::PC13, Edge, ExtiPin, Input},
     interrupt,
     prelude::*,
     stm32,
@@ -21,7 +21,7 @@ use cortex_m::{
 use rt::entry;
 
 // Set up global state. It's all mutexed up for concurrency safety.
-static BUTTON: Mutex<RefCell<Option<PC13<Input<PullUp>>>>> = Mutex::new(RefCell::new(None));
+static BUTTON: Mutex<RefCell<Option<PC13<Input>>>> = Mutex::new(RefCell::new(None));
 
 #[entry]
 fn main() -> ! {

examples/otg_fs_serial.rs

@@ -96,11 +96,11 @@ unsafe fn main() -> ! {
         pin_dm: gpioa
             .pa11
             .into_alternate(&mut gpioa.moder, &mut gpioa.otyper, &mut gpioa.afrh)
-            .set_speed(Speed::VeryHigh),
+            .speed(Speed::VeryHigh),
         pin_dp: gpioa
             .pa12
             .into_alternate(&mut gpioa.moder, &mut gpioa.otyper, &mut gpioa.afrh)
-            .set_speed(Speed::VeryHigh),
+            .speed(Speed::VeryHigh),
     };
 
     let usb_bus = UsbBus::new(usb, &mut EP_MEMORY);

examples/serial_vcom.rs

@@ -27,33 +27,33 @@ fn main() -> ! {
     let mut rcc = p.RCC.constrain();
     let mut pwr = p.PWR.constrain(&mut rcc.apb1r1);
     // let mut gpioa = p.GPIOA.split(&mut rcc.ahb2);
-    // let mut gpiob = p.GPIOB.split(&mut rcc.ahb2);
-    let mut gpiod = p.GPIOD.split(&mut rcc.ahb2);
+    let mut gpiob = p.GPIOB.split(&mut rcc.ahb2);
+    // let mut gpiod = p.GPIOD.split(&mut rcc.ahb2);
 
     // clock configuration using the default settings (all clocks run at 8 MHz)
     let clocks = rcc.cfgr.freeze(&mut flash.acr, &mut pwr);
     // TRY this alternate clock configuration (clocks run at nearly the maximum frequency)
     // let clocks = rcc.cfgr.sysclk(64.MHz()).pclk1(32.MHz()).freeze(&mut flash.acr);
 
-    //let tx = gpioa.pa2.into_af7(&mut gpioa.moder, &mut gpioa.afrl);
-    // let tx = gpiob.pb6.into_af7(&mut gpiob.moder, &mut gpiob.afrl);
-    let tx = gpiod
-        .pd5
-        .into_alternate(&mut gpiod.moder, &mut gpiod.otyper, &mut gpiod.afrl);
+    // let tx = gpioa.pa2.into_alternate(&mut gpioa.moder, &mut gpioa.otyper, &mut gpioa.afrl);
+    let tx = gpiob
+        .pb6
+        .into_alternate(&mut gpiob.moder, &mut gpiob.otyper, &mut gpiob.afrl);
+    // let tx = gpiod.pd5.into_alternate(&mut gpiod.moder, &mut gpiod.otyper, &mut gpiod.afrl);
 
-    // let rx = gpioa.pa3.into_af7(&mut gpioa.moder, &mut gpioa.afrl);
-    // let rx = gpiob.pb7.into_af7(&mut gpiob.moder, &mut gpiob.afrl);
-    let rx = gpiod
-        .pd6
-        .into_alternate(&mut gpiod.moder, &mut gpiod.otyper, &mut gpiod.afrl);
+    // let rx = gpioa.pa3.into_alternate(&mut gpioa.moder, &mut gpioa.otyper, &mut gpioa.afrl);
+    let rx = gpiob
+        .pb7
+        .into_alternate(&mut gpiob.moder, &mut gpiob.otyper, &mut gpiob.afrl);
+    // let rx = gpiod.pd6.into_alternate(&mut gpiod.moder, &mut gpiod.otyper, &mut gpiod.afrl);
 
     // TRY using a different USART peripheral here
-    let serial = Serial::usart2(
-        p.USART2,
+    let serial = Serial::usart1(
+        p.USART1,
         (tx, rx),
         Config::default().baudrate(115_200.bps()),
         clocks,
-        &mut rcc.apb1r1,
+        &mut rcc.apb2,
     );
     let (mut tx, mut rx) = serial.split();
 

examples/spi_dma_rxtx.rs

@@ -47,15 +47,15 @@ const APP: () = {
         let sck = gpiob
             .pb3
             .into_alternate(&mut gpiob.moder, &mut gpiob.otyper, &mut gpiob.afrl)
-            .set_speed(Speed::High);
+            .speed(Speed::High);
         let miso = gpiob
             .pb4
             .into_alternate(&mut gpiob.moder, &mut gpiob.otyper, &mut gpiob.afrl)
-            .set_speed(Speed::High);
+            .speed(Speed::High);
         let mosi = gpiob
             .pb5
             .into_alternate(&mut gpiob.moder, &mut gpiob.otyper, &mut gpiob.afrl)
-            .set_speed(Speed::High);
+            .speed(Speed::High);
         let mut dummy_cs = gpiob.pb6.into_push_pull_output_in_state(
             &mut gpiob.moder,
             &mut gpiob.otyper,

src/can.rs

@@ -20,38 +20,31 @@ pub trait Pins: sealed::Sealed {
 macro_rules! pins {
     ($($PER:ident => ($tx:ident<$txaf:literal>, $rx:ident<$rxaf:literal>),)+) => {
         $(
-            impl crate::can::sealed::Sealed for ($tx<crate::gpio::Alternate<PushPull, $txaf, >>, $rx<crate::gpio::Alternate<PushPull, $rxaf>>) {}
-            impl crate::can::Pins for ($tx<crate::gpio::Alternate<PushPull, $txaf, >>, $rx<crate::gpio::Alternate<PushPull, $rxaf>>) {
+            impl crate::can::sealed::Sealed for (crate::gpio::$tx<crate::gpio::Alternate<$txaf>>, crate::gpio::$rx<crate::gpio::Alternate<$rxaf>>) {}
+            impl crate::can::Pins for (crate::gpio::$tx<crate::gpio::Alternate<$txaf>>, crate::gpio::$rx<crate::gpio::Alternate<$rxaf>>) {
                 type Instance = $PER;
             }
         )+
     }
 }
 
 mod common_pins {
-    use crate::gpio::{
-        gpioa::{PA11, PA12},
-        gpiob::{PB8, PB9},
-        gpiod::{PD0, PD1},
-        PushPull,
-    };
     use crate::pac::CAN1;
 
     // All STM32L4 models with CAN support these pins
     pins! {
         CAN1 => (PA12<9>, PA11<9>),
-        CAN1 => (PD1<9>, PD0<9>),
         CAN1 => (PB9<9>, PB8<9>),
     }
+    #[cfg(not(any(feature = "gpio-l41x")))]
+    pins! {
+        CAN1 => (PD1<9>, PD0<9>),
+    }
 }
 
 // L4x1
 #[cfg(any(feature = "stm32l431", feature = "stm32l451", feature = "stm32l471"))]
 mod pb13_pb12_af10 {
-    use crate::gpio::{
-        gpiob::{PB12, PB13},
-        PushPull,
-    };
     use crate::pac::CAN1;
     pins! { CAN1 => (PB13<10>, PB12<10>), }
 }