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Add verible formatter for SystemVerilog #111

Add verible formatter for SystemVerilog

Add verible formatter for SystemVerilog #111

Triggered via pull request May 6, 2024 17:46
@stevearcstevearc
synchronize #391
Status Success
Total duration 12s
Artifacts

automation_request_review.yml

on: pull_request_target
request_review
2s
request_review
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