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Popular repositories Loading

  1. wb_sdram_ctrl wb_sdram_ctrl Public

    SDRAM controller with multiple wishbone slave ports

    Verilog 28 12

  2. i2s i2s Public

    i2s core, with support for both transmit and receive

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  3. ar100-info ar100-info Public

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  4. llvm-or1k llvm-or1k Public

    LLVM backend for OpenRISC 1000

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  5. diila diila Public

    A Device Independent Integrated Logic Analyzer

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  6. clang-or1k clang-or1k Public

    Clang for OpenRISC 1000

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