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Minutes20170303
- Date: 2017-03-03, 16:11
- Participants: Joe, Jason, Greg, Robert, Marcin, Samer, Thomas, Filip, Sébastien
- Minutes: Robert
- Chair: Joe
Greg gives short summary of how creotech team will work with WUT and responsibilities
Filip: Creotech has 10 engineers, HDL and software.
Marcin, Adrian, Filip: please introduce yourselves to M-Labs and physicists; contact info for Creotech guys is on the wiki https://github.com/m-labs/sinara/wiki/Team
Filip: Will be based on existing production test suites, adapting previous test suites for AMC-like projects. Direct and pragmatic approach.
Greg please give high level status of the following key PCBs. Field questions from physicists on timeline, testing. Focus on aspects that relate to WUT-Creotech interaction. Save specific questions for Greg until later in the discussion. PCB_Sayma_RTM PCB_Sayma_AMC PCB_Metlino
Greg: JESD SI, Issue #166:
- PCBs finished, SI pending.
- Expedition/Mentor Analyzer crashes do to naming. Eesolved now.
- 10 GHz JESD204B SI spec including margins to account for ideality approximations.
- ADC link at 8G looks good.
- DAC link tricky, 10G.
- Should use pre-emphasis, potentially also relax JESD spec down to DAC chip spec.
- All components (traces, connectors, routing) seem to contribute oon a similar level.
- Routing optimization mostly exploited.
- Greg suggests spending a bit more on tweaking and then relaxing to DAC spec + pre-emph.
Greg: production timeline:
- Verification of production files for Sayma AMC and RTM received. Changes being implemented. Metlino should not be a delay.
- In a few days production start AMC/RTM, three weeks production run.
- One week for tweaking layout, Four weeks production, Two weeks testing at WUT, i.e. shipping of prototypes to UMD etc in 7 weeks.
- Test boards all in production/finished. Will use Spartan devkit for testing.
M-Labs: What is status of WUT/Creotech collaboration with M-Labs to use Migen/ARTIQ to test connectivity of IC's on PCB, data integrity, etc?
M-Labs: AD9154 and SI5324 register maps that can be adapted to Sayma. Those will be passed on to WUT.
Creotech/WUT: to request existing register maps from M-Labs.
Oxford: is using the HMC440 narrowband PLL chip, no register map useful for HMC830.
Does Creotech have questions for physicists? Are there additional design constraints or clarifications needed for the work you're doing?
Marcin: Need for JESD core for testing.
Robert: offers the misoc JESD204b core, WUT/Creotech could reuse the verilog intermediate format.
Creotech engineers may leave call if they like.
- PCB_Sayma_RTM
- PCB_Sayma_AMC
- PCB_Metlino
See above.
allaki analog mezzanine: schematic review for analog input #165 allaki analog mezzanine: output design review #79 allaki schematic review catch all #110
Joe: would like to see simulations, i.e. impedance matching, cross talk simulations.
Samer: needs final component values for matching, especially analog input.
Joe: suggests matching the 10 V input to existing chips as planned. Other users/implementors need to follow and match those then.
Tom: INA will do +-10 out, then use resistive divider to match to ADC input and VCM.
Tom: suggests table of component population options i.e. tabulate DNPs/values for different options/effects.
Tom/Samer: Simulations for filters: Pole frequencies etc. verified and confirmed.
Samer: schematics style #110 should remain. #110, #165 mostly resolved. Individual items to be handled.
Switchable attenuator: 32 dB range deemed sufficient. Route DOUT back to AUX FPGA.
AUX ADC: hook up power detector temperature sensor if possible.
Homogenize coupling capacitors (some 10nF now). Use 10nF for DAC path except for one at the input to enable easy testing the difference.
Plan to implement the requested changes by the beginning of next week.
Samer: requests requestors to check his replies to their requests.
Tom: individual channel screening: looks very hard, no standard screens would fit. Custom screens would be complicated. Consensus is to not go for individual screens and test.
@filipswit What is status of documentation? You haven't registered opinion on documentation discussion. 133
@M-Labs how do you want to handle updating github/m-labs/artiq-hardware and moving to sinara repository?
M-Labs: Kasli documentation work in progress.
M-Labs: will prioritize backplane description/freeze for Tom. Greg: suggests MLVDS backplane plus clocks. Agreed upon. Tom will copy-paste suggestion from #129 into the Wiki.
Is PCB_mezzanine_clock ready for transfer to WUT? https://github.com/m-labs/sinara/issues/93
Prototype built and tested to match simulation. Problems with magnetic pickup. Need Highpass after balun. Does not fit mezzanine form factor yet. But design can be handed off to WUT.
Reduced use case now that the HMC830 is on Sayma RTM. Use case for Oxford is LO for Ca upconversion gaining maybe 10 dB at certain frequencies.
Joe requests packaging and manufacture by WUT. USeful for Kasli/DDS etc. Tom will pass on design. Limitation: HMC440 PLL chip only goes up to 2.4 GHz.
What clocking scheme does Oxford plan to use at outset? M-Labs would like to identify the bare bones clock configuration for testing of v0.1 hardware.
Short term: KC705, 100 MHz SMA into Sayma SMA
Longer term: Full Metlino + Sayma with RF backplane.
Oxford: DAC always 2.4 GHz with potential option of 2.0 GHz later. Different experiments. 600 MHz sample rate, 1000 MHz sample rate. Mix mode potentially, coarse modulation.
UMD: DAC, 1 GHz, 2 GHz, no need for 2.4 GHz.
M-Labs will start consolidating artiq-hardware and the clocking wiki page.
Lock-in of electrical interface for Kasli Carrier and VHDCI Carrier.
See above.
Is there a plan to build a 1 to 3 GHz analog mezzanine?
Allaki Balun limits to 4 GHz. Oxford plans IQ mixer mezzanine in conjuction with low noise LO from clock Mezzanine to get lower noise. TBD IQ mixer, 90 deg hybrid for SSB, not vector modulated. Probably won't fit a mixer on Allaki.
Samer suggests dropping power detectors. Could fit mixer instead.
Who wants to support PID support for Sayma?
JESD RX, ADC, PID: UMD no need.
- Robert: important, weekly/biweekly
- Jason: important, biweekly
- Samer: important, biweekly
- NIST via Joe: only Allaki, shift by +2 hours.
- Tom: biweekly/weekly
- Greg: weekly
- Joe: weekly/biweekly?