EEM
Eurocard Extension Module (EEM) is a Sinara standard for low-cost, low-bandwidth peripherals that are controlled by ARTIQ DRTIO.
EEM peripherals are supplied with power and a digital interface (ARTIQ DRTIO) from an EEM Carrier, such as Kasli, via ribbon cables using the EEM Connector interface.
EEM peripheral PCBs are
- 100 mm tall
- up to 160 mm long
EEM Carriers provide EEM Connectors to supply EEM peripherals with power and digital IO. Presently, Sinara includes two EEM Carriers:
- Kasli Carrier can serve as a stand-alone ARTIQ Master that generates DRTIO signals
- VHDCI Carrier interfaces with Sayma or Metlino boards that generate DRTIO signals
EEM connectors provide a standardised means of connecting EEM peripherals to a carrier, such as Kasli, which provides power and real-time digital IO (DRTIO).
Connectors are 2x15 100mil pitch male pin-header (pinout below). Wiring between boards is typically done using ribbon cable (50mil wire pitch).
Connector pinout:
| Function | Comment | Pin(s) | pin designation if used for SPI | RJ45 SPI |
|---|---|---|---|---|
| GND | 1, 4, 7, 10, 13, 16, 19, 22, 25 | |||
| +12V | 2A max (5A max for all EEM+Kasli/VHDCI together) | 28, 29 | ||
| +3V3 | 20mA max, managmenet power for EEPROMs etc | 30 | ||
| I2C | 3V3 LVCMOS | 26 (SDA), 27 (SCL) | ||
| LDVS_1 | LVDS, bi-directional | 2 (P), 3 (N) | SCLK0, clock-capable | SCLK0, clock-capable |
| LDVS_2 | LVDS, bi-directional | 5 (P), 6 (N) | MOSI | MOSI0 |
| LDVS_3 | LVDS, bi-directional | 8 (P), 9 (N) | MISO | MISO0 |
| LDVS_4 | LVDS, bi-directional | 11 (P), 12 (N) | CS0 | CS0 |
| LDVS_5 | LVDS, bi-directional | 14 (P), 15 (N) | CS1 | SCLK1 |
| LDVS_6 | LVDS, bi-directional | 17 (P), 18 (N) | MOSI1 | |
| LDVS_7 | LVDS, bi-directional | 20 (P), 21 (N) | MISO1 | |
| LDVS_8 | LVDS, bi-directional | 23 (P), 24 (N) | CS1 |
| odd | even | ||
|---|---|---|---|
| 1 | GND | 0P | 2 |
| 3 | 0N | GND | 4 |
| 5 | 1P | 1N | 6 |
| 7 | GND | 2P | 8 |
| 9 | 2N | GND | 10 |
| 11 | 3P | 3N | 12 |
| 13 | GND | 4P | 14 |
| 15 | 4N | GND | 16 |
| 17 | 5P | 5N | 18 |
| 19 | GND | 6P | 20 |
| 21 | 6N | GND | 22 |
| 23 | 7P | 7N | 24 |
| 25 | GND | SDA | 26 |
| 27 | SCL | 12V | 28 |
| 29 | 12V | MP | 30 |
LVDS is compatible with 1.8V, 2.5 and 3.3V bank supply. Metlino utilises 1.8V FPGA bank supply, while Kasli utilises 2.5V supply.
Each EEM peripheral has an EEPROM on its I2C bus for identification.
Multiple digital IO protocols are supported for the LVDS lines on each EEM Connector. Protocol choice is baked-in when the ARTIQ Master FPGA's bitstream is compiled.
- TTLs, input, output, bidirectional
- SPI
- SPI Phys have the pin assignment: SCLK, MOSI, MISO, CS in that order.
- NU-Servo fast ADC/DDS/PID
- CameraLink
See ARTIQ #823 for the bitstream and device_db building infrastructure requirements.
The old idea of having a restricted set of pprotocols that could be chosen at runtime (see issue #164 for discussion) has been abandoned.
EEM PCBs are designed to mount either in a stand-alone enclosure, or in a 19'' rack. If in a rack,
- pitch is 12 HP ("wide") or 4 HP ("narrow").
Suitable enclosures:
- Standard frame enclosures like this one
- https://www.amazon.com/1455N-Silver-Aluminum-Sized-Guide/dp/B004RIKZ6A
- http://pixustechnologies.com/products/custom-chassis-solutions-4/instrumentation-cases/versatile-series/
- http://uk.farnell.com/vero/114-52008l/case-eurocard-3u-6hp/dp/1277439
- http://www.srs-products.co.uk/netcase.htm
- http://uk.rs-online.com/web/p/rack-panels/1866766/
Suitable racks:
Following is a summary of a proposed backplane. Note that presently there is no officially supported EEM backplane (only the EEM Connectors).
The 96 position DIN 41612 connector from Kasli should be used to supply backplane-compatible EEMs or a breakout board for more EEM connectors. Supporting the backplane from an EEM is optional. Depending on electrical simplicity an EEM could opt to support an EEM Connector interface and backplane signaling as a runtime alternative, or as a fixed design choice.
The equivalent of four EEMs is supplied from Kasli through the backplane. Whether these four backplane EEMs are in addition to the eight EEM Connectors s or mutually exclusive with them remains TBD. The backplane is passive.
- 1 pin: 3.3 V management power
- 2 pins: 12 V
- 3 pins: GND
- 4x2 (1 pair per EEM): provide a reference clock signal to EEMs
- 4x2 (2 per EEM): I2C
- 4x2x8 (8 LVDS pairs per EEM)
- 10 pins remaining for more power/GND
The signals are star-routed to several EEM DIN 41612 connectors in a barrel-shifted way so that a single EEM can claim up to four EEM links. The EEM connector pinout should be the same as Kasli. The four CLK/I2C/LVDS groups should be assigned in two different ways.
If the unused LVDS and clock stubs are not a problem, the backplane layout could be a very flexible routing (where 4-link EEMs can be plugged into any slot) or a more fixed routing (but with no stub problems).
- 0: 0, 1, 2, 3 (Kasli)
- 1: 0, 1, 2, 3 (up to quad-link EEM)
- 2: 1, 2, 3 (up to triple-link EEM)
- 3: 2, 3 (up to double-link EEM)
- 4: 3 (single-link EEM)
The EEM pitch should such that a 19 inch subrack can be filled. Then if e.g. a single-link EEM is pliugged into slot 1, it will claim only link 1 and all slots to the right (2-4) can be used. A double-link EEM plugged into slot 3 would claim links 2 and 3 and slot 4 can not be used. An N-link EEM requires that the N-1 slots to the right of it are empty.
- 0: 0, 1, 2, 3
- 1: 1, 2, 3, 0
- 2: 2, 3, 0, 1
- 3: 3, 0, 1, 2
- 4: 0, 1, 2, 3
- 5: 1, 2, 3, 0
- 6: 2, 3, 0, 1
- etc.
The pitch between connectors on the backplane can e.g. be 4 HP. If e.g. Kasli is plugged into slot 0, it drives all four groups from there. Then if e.g. a single-link EEM is pliugged into slot 1, it will claim only link 1. A double-link EEM plugged into slot 6 would claim links 2 and 3. An N-link EEM requires that the N-1 slots to the right of it are empty.
To clean up the wiring in the rack, one could design a simple mezzanine for Kasli (or the VHDCI carrier) that plugs into its EEM Connectors (four or 8) and then routes them through another (or two) DIN connectors to the backplane. The backplane would then do all the wiring for EEMs significantly reducing the ribbon rats nest.