CPLD XC2C256-6FTG256C is EOL

[MorganTL]

No description provided.

[gkasprow]

any suggestion what family we could use here?

[Spaqin]

Mirny uses the same CPLD.

A suggestion would be to use Artix-7, like XC7A35TICSG324 or XC7A100TCSG324, depending if 35k logic cells would be fine or we need 100k.

[gkasprow]

Artix is FPGA, which means it has much higher internal delays and is suitable for synchronous designs. CPLD was placed here as a simple asynchronous glue logic. Such a big FPGA would significantly increase the board cost because we also need extra power rails.

[gkasprow]

Since AMD and Lattice do not make any CPLDs anymore, we can move to Cypres or Altera:
5M2210ZF256I5N
EPM570F256C4N
CY37256VP256-100BGC

@jordens Maybe the ICE40 family could be fine here?

[jordens]

That would be interesting to explore.

[kaolpr]

If there are no pending ideas on implementing some more elaborate logic we could go with iCE40 HX8K as in Fastino. This would let us drop LVDS transceivers too (same for Mirny).

[dnadlinger]

The biggest (in relative terms) design we currently need is the status readback for SUServo mode: quartiq/urukul#11. For this, we ran right up against the size limits of the parts that were on older revisions, at least in a straightforward implementation, though there is some discussion on how to best implement this in a glitch-free way still unresolved (see linked PR).

[dnadlinger]

(the amount of logic required is still very small; I suppose you could just run that PR through the iCE toolchain to check)

[jordens]

Is anybody working on this? I have no idea about stock situation at cti/ts. Given the revision/production/development/testing lead time this may be something that should have been started a while ago.

[gkasprow]

Yes. I expect to have Mirny and Urukul designs done in 2 months. Two guys are working on these designs.

[gkasprow]

CTI secured stocks for next year

[jordens]

Who is doing the gateware redesign? That should be done first to verify/decide the choice of chip (did you choose already?).

[gkasprow]

we will go for same chip as in Fastino

[pkozakiewicz]

I have no idea about stock situation at cti/ts.

We are well stocked with CPLDs and finished devices so this situation does not threaten availability.