riscv: define mtvec CSR with macro helpers #252
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Changes the macro argument type to `expr` to allow using constants, expressions, and other initializers for CSR mask values.
Ignores the warning for the `clippy::identity_op` to allow using ranged bitfield CSR macro arguments with a leading `0`.
riscv/src/register/mtvec.rs
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| /// The address is aligned to 4-bytes. | ||
| #[inline] | ||
| pub fn trap_mode(&self) -> Option<TrapMode> { | ||
| let mode = self.bits & 0b11; | ||
| match mode { | ||
| 0 => Some(TrapMode::Direct), | ||
| 1 => Some(TrapMode::Vectored), | ||
| _ => None, | ||
| } | ||
| pub fn set_address(&mut self, address: usize) { | ||
| self.bits = (address & !TRAP_MASK) | (self.bits & TRAP_MASK); |
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This 4-byte alignment is in reference to the CSR specification, however in riscv-rt::asm there is a reference to the trap table being 16-byte aligned.
Should we force 16-byte alignment here by masking the lower 4 bits?
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According to the RISCV Priv spec:
The value in the BASE field must always be aligned on a 4-byte boundary, and the MODE setting may impose additional alignment constraints on the value in the BASE field.
...
An implementation may have different alignment constraints for different modes. In particular, MODE=Vectored may have stricter alignment constraints than MODE=Direct. Allowing coarser alignments in Vectored mode enables vectoring to be implemented without a hardware adder circuit.
So, without additional information about the target, we can only ensure that BASE is 4-byte aligned. For further versions of riscv-rt, we can think of a mechanism to apply a custom alignment depending on the target. For example, the E310x chip expects 64-byte alignment when working in vectored mode.
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In this way, we can add a try_set_address that checks that base is at least 4-byte aligned
riscv/src/register/mtvec.rs
Outdated
| /// The address is aligned to 4-bytes. | ||
| #[inline] | ||
| pub fn trap_mode(&self) -> Option<TrapMode> { | ||
| let mode = self.bits & 0b11; | ||
| match mode { | ||
| 0 => Some(TrapMode::Direct), | ||
| 1 => Some(TrapMode::Vectored), | ||
| _ => None, | ||
| } | ||
| pub fn set_address(&mut self, address: usize) { | ||
| self.bits = (address & !TRAP_MASK) | (self.bits & TRAP_MASK); |
There was a problem hiding this comment.
According to the RISCV Priv spec:
The value in the BASE field must always be aligned on a 4-byte boundary, and the MODE setting may impose additional alignment constraints on the value in the BASE field.
...
An implementation may have different alignment constraints for different modes. In particular, MODE=Vectored may have stricter alignment constraints than MODE=Direct. Allowing coarser alignments in Vectored mode enables vectoring to be implemented without a hardware adder circuit.
So, without additional information about the target, we can only ensure that BASE is 4-byte aligned. For further versions of riscv-rt, we can think of a mechanism to apply a custom alignment depending on the target. For example, the E310x chip expects 64-byte alignment when working in vectored mode.
riscv/src/register/mtvec.rs
Outdated
| /// The address is aligned to 4-bytes. | ||
| #[inline] | ||
| pub fn trap_mode(&self) -> Option<TrapMode> { | ||
| let mode = self.bits & 0b11; | ||
| match mode { | ||
| 0 => Some(TrapMode::Direct), | ||
| 1 => Some(TrapMode::Vectored), | ||
| _ => None, | ||
| } | ||
| pub fn set_address(&mut self, address: usize) { | ||
| self.bits = (address & !TRAP_MASK) | (self.bits & TRAP_MASK); |
There was a problem hiding this comment.
In this way, we can add a try_set_address that checks that base is at least 4-byte aligned
Uses the CSR macro helpers to define the `mtvec` CSR register. Authored-by: rmsyn <[email protected]> Reviewed-by: romancardenas <[email protected]>
Adds basic unit-tests for the `mtvec` CSR.
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Looks like Clippy added new lints. @rmsyn could you address them? |
Uses the CSR macro helpers to define the
mtvecCSR register.Adds basic unit-tests for the
mtvecCSR.Ignores the warning for the
clippy::identity_opto allow using ranged bitfield CSR macro arguments with a leading0.Changes the macro argument type to
exprto allow using constants, expressions, and other initializers for CSR mask values.