Add unratified Smclic, Ssclic, Smclicshv extensions #420
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| _ => [v with Mode = o[Mode]] | ||
| } | ||
| } | ||
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| function haveSmclic() -> bool = mtvec[Mode] == 0b11 |
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haveFoo means Foo is available for use, not that its additions are currently being used. That is, haveSmclic means "is the model configured to provide the Smclic extension?", not "has software configured mtvec to use the CLIC?".
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I can change all places that say haveSmclic to SmclicMode. Is that acceptable?
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| val trapVectorMode_of_bits : tv_mode -> TrapVectorMode | ||
| function trapVectorMode_of_bits (m) = | ||
| match (m) { | ||
| 0b00 => TV_Direct, | ||
| 0b01 => TV_Vector, | ||
| 0b11 => TV_Smclic, |
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Only if you have the CLIC extension. Plus this is for all xtvec, not just mtvec.
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I see this in the Priv spec:
The mtvec register must always be implemented, but can contain a read-only value. If mtvec is
writable, the set of values the register may hold can vary by implementation. The value in the
BASE field must always be aligned on a 4-byte boundary, and the MODE setting may impose
additional alignment constraints on the value in the BASE field.
So just as TV_Vector may not be supported by an implementation, TV_Smclic may not be supported by an implementation. When @billmcspadden-riscv adds WARL config support to the riscv-sail model, TV_Smclic WARL support can be handled the same way as TV_Vector. So I think it is incorrect to say "only if you have the CLIC extension". CLIC extension is defined as just another mtvec mode which is labeled Reserved in the current priv spec.
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Well there's a bit of a distinction though. Direct and Vectored are both specified as what mtvec.BASE=0/1 mean, with >=2 reserved. Whereas this CLIC encoding is specified in its own extension on top of the base privileged spec. That is, the philosophical distinction is that vectored is part of the base privileged spec but may not be supported, whereas CLIC support is its own named extension on top.
Spec: https://github.com/riscv/riscv-fast-interrupt
Tests: riscv-non-isa/riscv-arch-test#436
Note: pulls are not yet available for spike that support CLIC
Related pulls to run arch-tests against the sail-riscv model:
riscv-software-src/riscv-config#169
riscv-software-src/riscof#106
riscv-software-src/riscv-isa-sim#1596
To include m-mode CLIC interrupt tests in riscof testlist flow, add Smclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
ISA: RV32IMCZicsr_Zifencei_Smclic