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EPS V1.0 Complete
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@rgw3d
rgw3d committed Nov 3, 2020
1 parent f70fe12 commit 1baf0f2
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3 changes: 3 additions & 0 deletions .gitignore
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Expand Up @@ -28,3 +28,6 @@ fp-info-cache

# Other
*.png
*.gbr
*.drl
*.gbrjob
66 changes: 9 additions & 57 deletions avionics_board/DEBUG_INTERFACE.sch
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Expand Up @@ -23,69 +23,17 @@ Text Notes 950 4700 0 50 ~ 0
JTAG \n TDI (Test Data In)\n TDO (Test Data Out)\n TCK (Test Clock)\n TMS (Test Mode Select)\n TRST (Test Reset) optional.
Text Notes 2375 4525 0 50 ~ 0
SWD\n SWCLK (Clock signal to target CPU)\n SWDIO (Bi-directional data pin)\n SWO (Serial Wire output) optional
Wire Wire Line
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Expand Down Expand Up @@ -114,7 +62,7 @@ U 1 1 5EB9A283
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F 5 "https://www.digikey.com/product-detail/en/sullins-connector-solutions/PREC004SBAN-M71RC/S1112EC-04-ND/2774930" H 8375 4175 50 0001 C CNN "Order"
Expand Down Expand Up @@ -417,7 +365,7 @@ U 1 1 5EB6FE31
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Expand All @@ -435,8 +383,6 @@ F 5 "https://www.mouser.com/ProductDetail/Susumu/RR0816Q-49R9-D-68R?qs=sGAEpiMZZ
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Expand Down Expand Up @@ -539,4 +485,10 @@ Wire Notes Line width 20
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Wire Notes Line width 20
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189 changes: 89 additions & 100 deletions avionics_board/MRAM.sch
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Expand Up @@ -40,45 +40,26 @@ F 5 "https://www.digikey.com/product-detail/en/everspin-technologies-inc/MR25H10
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Text Notes 4860 3590 0 50 ~ 0
WP is write protect. Low active\nHOLD suspends operation. Low active. Only available when CS is low\nCS is chip select. Low active\nSCK is SPI cock\nSO is output\nSI is input\nVDD is from 3.0V to 3.6V\nConnect pad only to VSS\n\nhttps://www.cypress.com/file/196526/download for layout guide \n\n0.1uF decoupling cap
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Wire Wire Line
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Layout Note: Decoupling\n
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Expand All @@ -103,30 +84,6 @@ Wire Wire Line
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Expand All @@ -146,8 +103,6 @@ Wire Wire Line
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Text Notes 6975 5125 0 50 ~ 0
For AEC-Q100 & 4MB use: MR25H40MDF. Triple the price
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Expand Down Expand Up @@ -268,4 +178,83 @@ F 5 "https://www.digikey.com/en/products/detail/stackpole-electronics-inc/RMCF06
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