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Add STM32C0/G0/L0 ADC driver #94
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Signed-off-by: Gerson Fernando Budke <[email protected]>
The STM32_ADC_Common define the 0xC4 address for ADC_CALFACT register. This is only valid for the most advanced version of adc peripheral which is not compatible with the low cost devices like C0/G0/L0. This add a selector at class instanciation to allow the correct definition of the address. Signed-off-by: Gerson Fernando Budke <[email protected]>
Add mising ADVREGEN tag bit from ADC_CR register. Signed-off-by: Gerson Fernando Budke <[email protected]>
Signed-off-by: Gerson Fernando Budke <[email protected]>
Rename EOSEQ to EOS in ADC_ISR register to be compliance with C0/F0/G0/L0/WBA. Signed-off-by: Gerson Fernando Budke <[email protected]>
The STM32L0 ADC still in a loop waiting the calibration phase finish. This implement the calibration interrupt to finish calibration procedure and allow ADC driver to work. Signed-off-by: Gerson Fernando Budke <[email protected]>
Signed-off-by: Gerson Fernando Budke <[email protected]>
The STM32G0 ADC still in a loop waiting the channel config be ready. This implement the Channel Config Ready interrupt to based on CHSELRMOD and SCANDIR changes to allow ADC driver to work. Signed-off-by: Gerson Fernando Budke <[email protected]>
Signed-off-by: Gerson Fernando Budke <[email protected]>
Signed-off-by: Gerson Fernando Budke <[email protected]>
Signed-off-by: Gerson Fernando Budke <[email protected]>
Signed-off-by: Gerson Fernando Budke <[email protected]>
Cc: @mateusz-holenko |
Is there anything in particular that is delaying this PR from being completed? It has been over 2 months. |
Hi @tyler-macinnis , We synced 2 weeks ago with Renode team and we are waiting decision about possible API changes. After that we may apply a few changes, if necessary, but I believe this will start to move forward soon. |
I am confused here... Its been two months since what? Can you elaborate on what company/project you represent? This whole discussion is weird. You all seem to be working on some project that I (nor anyone else in my company) am not aware of. We will reach out (over email) to @nandojve since we know each other from Zephyr Project so that there is a possibility to get additional context, but if the tone here and the pressure (passive aggressive complaints or CCing people) will not change then I will close just this PR... |
@pgielda, @nandojve, and I (@otavio) work for O.S. Systems. @tyler-macinnis is a community user who seems to be affected by the same issue that @nandojve and I resolved. We didn't want to appear impolite. |
I meant that it had been two months since this last message. I was just curious about the current state/progress of this PR since it will indeed resolve an issue I am affected by as well. |
Well pinging a random person on github was never a way to achieve a result. @mateusz-holenko (nor anyone from the Renode team) has no clue who @otavio is... Opening a PR is enough, no need to ping us, especially specific random engineers... It will be looked at when its looked at... |
Just so that its clear @tyler-macinnis, this is an external PR, so there is no timeline. None of the people in this discussion (apart from me) are from the Renode team. But we do plan to address ADCs for more STM32 platforms at some point, but also tons of other things that are planned that might be more important... Unfortunately there is 10x more stuff to be done than time. Having said that Renode does allow to load peripheral code in runtime so you can just download those and load them in runtime in your scripts. (just do "include @/path/to/file.cs" in your resc script and Renode will compile and load the code). |
This fixes all open issues that blocks the STM32 ADC to run in the C0/G0/L0 devices. The related issues are:
This was tested using Zephyr mainline using https://github.com/zephyrproject-rtos/zephyr/tree/main/samples/drivers/adc sample using the following branch https://github.com/nandojve/zephyr/tree/renode/fix_stm32_c0g0l0_adc.
Assuming the renode already in the path the below command allow build and run the simulation.
depends on antmicro/dts2repl#6 and antmicro/dts2repl#5