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PyMTL 4.0 release staging #237

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488093e
Rename basic_rtl to primitive
ptpan Aug 26, 2022
6584709
[WIP] Stream and dstruct
ptpan Aug 28, 2022
60d73b5
[WIP] StreamSrc/Sink test passing
ptpan Aug 28, 2022
5778a40
[WIP] example and stdlib unit tests passing
ptpan Aug 29, 2022
686db8c
[WIP] Remove out dated tests
ptpan Aug 29, 2022
6f12baf
Remove TestMasterCL
ptpan Aug 29, 2022
406ff8c
Add back the RTL-FL adapters
ptpan Aug 31, 2022
bed393f
Split adapter implementation into single files
ptpan Aug 31, 2022
519c711
Hold stream source when current message is None
ptpan Sep 8, 2022
25c3751
Add line_trace to I/OStreamIfc
ptpan Sep 8, 2022
b72cdea
[ProcFL] Add back ProcFL with adapters
ptpan Sep 10, 2022
3a6a375
get tests running on ProcFL
cbatten Sep 12, 2022
9834cc8
forgot to commit this update
cbatten Sep 12, 2022
4f5a8b1
add random delays to src/sink
cbatten Sep 22, 2022
a70db04
[dev] Add py module to dependency
ptpan Oct 26, 2022
6db6cee
add ordered option to stream sink
cbatten Nov 27, 2022
326559e
temporary fix to change mem msg type field to 3bits
cbatten Dec 1, 2022
37882bc
Fixing double/single underscore issue in translation
ptpan Feb 27, 2023
0e81097
Add non-blocking stream FL adapters
ptpan Mar 1, 2023
0eab5e3
Exposing stream-to-FL adapters in stdlib.stream
ptpan Mar 2, 2023
85300ff
Add line trace to stream-to-FL adapters
ptpan Mar 2, 2023
661c0bd
[mem] Add INV and FLUSH support to MemoryFL
ptpan Oct 26, 2022
86500e9
[mem] Add error message to out-of-bound accesses
ptpan Oct 27, 2022
8c961c7
[verilator] Force signals to toggle on posedge CLK
ptpan Oct 27, 2022
a27b176
[verilator] Add support for verilator 4.228
ptpan Oct 27, 2022
77e708d
[verilator] Update use of verilator variable name in C wrapper
ptpan Oct 27, 2022
cf51f50
[test] Fix segfault due to same toplevel name
ptpan Oct 27, 2022
d628f6a
[test] Temporarily disable tests in yosys backend
ptpan Nov 1, 2022
151edf5
[mem] Improve error messages for behavioral mem
ptpan Nov 22, 2022
fdaaad2
[error msg] Add error messages for double configuring a model
ptpan Nov 22, 2022
fbaa10c
src_file: defaults to filename where class is defined
ptpan Dec 8, 2022
fbb982c
[verilator] Use Verilator context in C/Python wrapper
ptpan Oct 23, 2023
6f0f52f
[import] Release line trace string at final
ptpan Oct 23, 2023
44002c1
[import] Use linker version script to avoid UNIQUE symbols
ptpan Oct 25, 2023
b034129
[import] Fix segfault on exit in import line trace test
ptpan Oct 26, 2023
e837b43
[gitignore] Ignore dist directory
ptpan Nov 2, 2023
e619c4a
[verilog] Refactor translation pass
ptpan Oct 12, 2023
e6fcf7d
[verilog] Use tempfile library to create tmp files
ptpan Oct 12, 2023
27e36b4
[verilog] Initial xdist support in translation/import
ptpan Oct 12, 2023
d4d0d6a
[xdist] Support parallel Verilog co-sim
ptpan Nov 2, 2023
777ea4d
[import] Set Verilog import to verbose
ptpan Nov 2, 2023
d9b4efa
[import] Remove optimization flags from g++ command
ptpan Nov 23, 2023
06174c3
[import] Update C++/Python wrapper to avoid unloading the shared lib
ptpan Nov 23, 2023
2ccab35
[unit-test] Use unique DUT class name to facilitate import
ptpan Nov 23, 2023
77ae1e1
[import] Fix variable reference in C++ wrapper
ptpan Nov 23, 2023
8647882
[dependency] Add fasteners to dependency
ptpan Nov 23, 2023
6b3997c
[ci] Upgrade to Verilator 5.016 in CI
ptpan Nov 23, 2023
609e454
[ci] Remove VERILATOR_ROOT var in CI script
ptpan Nov 23, 2023
2f023d5
[ci] Create symlink to Verilator include directory
ptpan Nov 23, 2023
a317ae8
[ci] Split Verilog and Yosys backend runs
ptpan Nov 23, 2023
c1e2dfb
[ci] Fix Yosys test path
ptpan Nov 23, 2023
1e97cfd
[stdlib] Set mem msg field type_ to its correct width
ptpan Nov 23, 2023
9e365e4
[ci] Fix Yosys test path
ptpan Nov 23, 2023
d573db8
[ci] Merge coverage reports between pytest runs
ptpan Dec 6, 2023
9ee08a5
[yosys] Deprecate use of yosys backend in examples/
ptpan Dec 6, 2023
0edc9a7
[err_msg] Use better message when slicing on Bitstruct signals
ptpan Dec 6, 2023
14d2282
Merge pull request #259 from pymtl/pp482-error-msg-slicing-non-bits
ptpan Dec 6, 2023
c23a673
[README] Point users to compile Verilator v5.016
ptpan Dec 6, 2023
8e546d8
[dsl] Add support for non-s args to refer to self
ptpan Dec 7, 2023
02b17d7
[dsl] Fix typo
ptpan Dec 7, 2023
0738bb7
Merge pull request #260 from pymtl/pp482-construct-self
ptpan Dec 7, 2023
0be16f7
[yosys] Deprecate yosys backend
ptpan Dec 7, 2023
512557d
[coverage] Disable couldnt-parse coverage warning
ptpan Dec 7, 2023
58ea59a
[test] Remove return values from mamba unit tests
ptpan Dec 7, 2023
7e55309
[import] Fix data type declaration for signals of different widths
ptpan Dec 7, 2023
7ce58d5
[setup] Add fasteners to dependency
ptpan Dec 7, 2023
c8e2ab5
[import] Use explicitly sized uint types for signal declaration
ptpan Dec 7, 2023
aa19bfb
[rtlir] Add visit_Constant to behavioral visitor
ptpan Dec 7, 2023
824ee65
[test] Use variable instead of int in extslice test case
ptpan Dec 7, 2023
6da7397
[test] Fix visit_Str test
ptpan Dec 7, 2023
1bf1b7d
[import] Add an import test that uses assertion
ptpan Dec 7, 2023
25c0752
[import] Implement Verilator assertion failure without aborting process
ptpan Dec 7, 2023
8084e12
Merge pull request #262 from pymtl/pp482-vl-assertion
ptpan Jan 29, 2024
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add random delays to src/sink
  • Loading branch information
cbatten authored and ptpan committed Nov 23, 2023
commit 4f5a8b18fe66bdc0c7524019b2f0b5d7f7f1b0be
8 changes: 7 additions & 1 deletion pymtl3/stdlib/stream/StreamSinkFL.py
Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,8 @@
Date : Aug 26, 2022
"""

from random import randint

from pymtl3 import *
from .ifcs import IStreamIfc

Expand All @@ -21,6 +23,7 @@ class PyMTLTestSinkError( Exception ): pass
class StreamSinkFL( Component ):

def construct( s, Type, msgs, initial_delay=0, interval_delay=0,
interval_delay_mode='fixed',
arrival_time=None, cmp_fn=lambda a, b : a == b ):

# Interface
Expand Down Expand Up @@ -103,7 +106,10 @@ def up_sink():
)

s.idx += 1
s.count = interval_delay
if ( interval_delay_mode == 'random' ):
s.count = randint(0,interval_delay)
else:
s.count = interval_delay

if s.count > 0:
s.count -= 1
Expand Down
9 changes: 7 additions & 2 deletions pymtl3/stdlib/stream/StreamSourceFL.py
Original file line number Diff line number Diff line change
Expand Up @@ -9,14 +9,16 @@
"""
from collections import deque
from copy import deepcopy
from random import randint

from pymtl3 import *
from .ifcs import OStreamIfc


class StreamSourceFL( Component ):

def construct( s, Type, msgs, initial_delay=0, interval_delay=0 ):
def construct( s, Type, msgs, initial_delay=0, interval_delay=0,
interval_delay_mode='fixed' ):

# Interface

Expand All @@ -41,7 +43,10 @@ def up_src():
else:
if (s.ostream.val & s.ostream.rdy) or s.prev_is_none:
s.idx += 1
s.count = interval_delay
if ( interval_delay_mode == 'random' ):
s.count = randint(0,interval_delay)
else:
s.count = interval_delay

if s.count > 0:
s.count -= 1
Expand Down
35 changes: 21 additions & 14 deletions pymtl3/stdlib/stream/test/src_sink_test.py
Original file line number Diff line number Diff line change
Expand Up @@ -52,27 +52,34 @@ def line_trace( s ):


@pytest.mark.parametrize(
('Type', 'msgs', 'src_init', 'src_intv',
'sink_init', 'sink_intv', 'arrival_time' ),
('Type', 'msgs', 'src_init', 'src_intv', 'src_mode',
'sink_init', 'sink_intv', 'sink_mode', 'arrival_time' ),
[
( Bits16, bit_msgs, 0, 0, 0, 0, arrival0 ),
# ( int, int_msgs, 10, 0, 0, 0, arrival1 ),
( Bits16, bit_msgs, 10, 1, 0, 0, arrival2 ),
( Bits16, bit_msgs, 10, 0, 0, 1, arrival3 ),
( Bits16, bit_msgs, 3, 4, 5, 3, arrival4 )
( Bits16, bit_msgs, 0, 0, 'fixed', 0, 0, 'fixed', arrival0 ),
( Bits16, bit_msgs, 10, 1, 'fixed', 0, 0, 'fixed', arrival2 ),
( Bits16, bit_msgs, 10, 0, 'fixed', 0, 1, 'fixed', arrival3 ),
( Bits16, bit_msgs, 3, 4, 'fixed', 5, 3, 'fixed', arrival4 ),
( Bits16, bit_msgs, 0, 10, 'random', 0, 0, 'fixed', None ),
( Bits16, bit_msgs, 0, 40, 'random', 0, 0, 'fixed', None ),
( Bits16, bit_msgs, 0, 0, 'fixed', 0, 10, 'random', None ),
( Bits16, bit_msgs, 0, 0, 'fixed', 0, 40, 'random', None ),
( Bits16, bit_msgs, 0, 10, 'random', 0, 10, 'random', None ),
( Bits16, bit_msgs, 0, 40, 'random', 0, 40, 'random', None ),
]
)
def test_src_sink_rtl( Type, msgs, src_init, src_intv,
sink_init, sink_intv, arrival_time ):
def test_src_sink_rtl( Type, msgs, src_init, src_intv, src_mode,
sink_init, sink_intv, sink_mode, arrival_time ):
th = TestHarnessSimple( Type, StreamSourceFL, StreamSinkFL, msgs, msgs )
th.set_param( "top.src.construct",
initial_delay = src_init,
interval_delay = src_intv,
initial_delay = src_init,
interval_delay = src_intv,
interval_delay_mode = src_mode,
)
th.set_param( "top.sink.construct",
initial_delay = sink_init,
interval_delay = sink_intv,
arrival_time = arrival_time,
initial_delay = sink_init,
interval_delay = sink_intv,
interval_delay_mode = sink_mode,
arrival_time = arrival_time,
)
run_sim( th )

Expand Down