src_file: defaults to filename where class is defined

pymtl · Dec 8, 2022 · 7c77d5b · 7c77d5b
1 parent 7dc425a
commit 7c77d5b
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Showing 3 changed files with 23 additions and 2 deletions.
diff --git a/pymtl3/passes/backends/verilog/VerilogPlaceholderPass.py b/pymtl3/passes/backends/verilog/VerilogPlaceholderPass.py
@@ -131,8 +131,14 @@ def setup_default_configs( s, m, irepr ):
       # Only try to infer the name of Verilog source file if both
       # flist and the source file are not specified.
       if not cfg.src_file and not cfg.v_flist:
-        parent_dir = os.path.dirname(inspect.getfile(m.__class__))
-        cfg.src_file = f"{parent_dir}{os.sep}{cfg.top_module}.v"
+        # parent_dir = os.path.dirname(inspect.getfile(m.__class__))
+        # cfg.src_file = f"{parent_dir}{os.sep}{cfg.top_module}.v"
+
+        # Use the file in which m.__class__ is defined as src_file.
+        file_path = os.path.abspath(inspect.getfile(m.__class__))
+        parent_dir = os.path.dirname(file_path)
+        module_name = os.path.splitext(os.path.basename(file_path))[0]
+        cfg.src_file = f"{parent_dir}{os.sep}{module_name}.v"
 
       # What is the original file/flist of the pickled source file?
       if cfg.src_file:

diff --git a/pymtl3/passes/backends/verilog/import_/test/ImportedObject_test.py b/pymtl3/passes/backends/verilog/import_/test/ImportedObject_test.py
@@ -47,6 +47,7 @@ def construct( s ):
           s.clk : "clk", s.reset : "reset",
           s.in_ : "d",   s.out : "q",
       } )
+      s.set_metadata( VerilogPlaceholderPass.src_file, dirname(__file__)+'/VReg.v' )
   a = VReg()
   a._tvs = [
     [    1,    '*' ],
@@ -71,6 +72,7 @@ class VUninit( Component, VerilogPlaceholder ):
     def construct( s ):
       s.in_ = InPort( Bits32 )
       s.out = OutPort( Bits32 )
+      s.set_metadata( VerilogPlaceholderPass.src_file, dirname(__file__)+'/VUninit.v' )
       s.set_metadata( VerilogPlaceholderPass.port_map, {
           s.in_ : "d", s.out : "q",
       } )
@@ -98,6 +100,7 @@ def construct( s ):
       s.in_ = InPort( Bits32 )
       s.out = OutPort( Bits32 )
 
+      s.set_metadata( VerilogPlaceholderPass.src_file, dirname(__file__)+'/VReg.v' )
       s.set_metadata( VerilogPlaceholderPass.port_map, {
           s.in_ : "d",   s.out : "q",
       } )
@@ -132,6 +135,7 @@ def construct( s ):
       s.cin = InPort( Bits1 )
       s.out = OutPort( Bits32 )
       s.cout = OutPort( Bits1 )
+      s.set_metadata( VerilogPlaceholderPass.src_file, dirname(__file__)+'/VAdder.v' )
   a = VAdder()
   a._tvs = [
     [    1,      1,     1,     3, 0 ],
@@ -165,6 +169,7 @@ def construct( s, data_width, num_entries, count_width ):
       s.enq_en  =  InPort( Bits1  )
       s.enq_rdy = OutPort( Bits1  )
       s.enq_msg =  InPort( mk_bits( data_width ) )
+      s.set_metadata( VerilogPlaceholderPass.src_file, dirname(__file__)+'/VQueue.v' )
   num_entries = 1
   q = VQueue(
       data_width = 32,
@@ -264,6 +269,7 @@ def construct( s, data_width, num_entries, count_width ):
       s.count = OutPort( mk_bits( count_width )  )
       s.deq   = DequeueIfc( mk_bits( data_width ) )
       s.enq   = EnqueueIfc( mk_bits( data_width ) )
+      s.set_metadata( VerilogPlaceholderPass.src_file, dirname(__file__)+'/VQueue.v' )
   num_entries = 1
   q = VQueue(
       data_width = 32,
@@ -297,6 +303,7 @@ class VPassThrough( Component, VerilogPlaceholder ):
     def construct( s, nports, nbits ):
       s.in_ = [ InPort( mk_bits(nbits) ) for _ in range(nports) ]
       s.out = [ OutPort( mk_bits(nbits) ) for _ in range(nports) ]
+      s.set_metadata( VerilogPlaceholderPass.src_file, dirname(__file__)+'/VPassThrough.v' )
       s.set_metadata( VerilogPlaceholderPass.params, {
           'num_ports' : nports,
           'bitwidth'  : nbits,
@@ -328,6 +335,7 @@ class VPassThrough( Component, VerilogPlaceholder ):
     def construct( s, nports, nbits ):
       s.in_ = [ InPort( mk_bits(nbits) ) for _ in range(nports) ]
       s.out = [ OutPort( mk_bits(nbits) ) for _ in range(nports) ]
+      s.set_metadata( VerilogPlaceholderPass.src_file, dirname(__file__)+'/VPassThrough.v' )
       s.set_metadata( VerilogPlaceholderPass.params, {
           'num_ports' : nports,
           'bitwidth'  : nbits,
@@ -353,6 +361,7 @@ class VPassThrough( Component, VerilogPlaceholder ):
     def construct( s, nports, nbits ):
       s.in_ = [ InPort( mk_bits(nbits) ) for _ in range(nports) ]
       s.out = [ OutPort( mk_bits(nbits) ) for _ in range(nports) ]
+      s.set_metadata( VerilogPlaceholderPass.src_file, dirname(__file__)+'/VPassThrough.v' )
       s.set_metadata( VerilogPlaceholderPass.params, {
           'num_ports' : nports,
           'bitwidth'  : nbits,
@@ -400,6 +409,7 @@ class VReg( Component, VerilogPlaceholder ):
     def construct( s ):
       s.in_ = InPort( Bits32 )
       s.out = OutPort( Bits32 )
+      s.set_metadata( VerilogPlaceholderPass.src_file, dirname(__file__)+'/VReg.v' )
       s.set_metadata( VerilogPlaceholderPass.port_map, {
           s.in_ : "d", s.out : "q",
       } )
@@ -433,6 +443,7 @@ class VRegTrace( Component, VerilogPlaceholder ):
     def construct( s ):
       s.in_ = InPort( Bits32 )
       s.out = OutPort( Bits32 )
+      s.set_metadata( VerilogPlaceholderPass.src_file, dirname(__file__)+'/VRegTrace.v' )
       s.set_metadata( VerilogPlaceholderPass.port_map, {
           s.in_ : "d", s.out : "q",
       } )
@@ -464,6 +475,7 @@ class VRegTrace( Component, VerilogPlaceholder ):
     def construct( s ):
       s.in_ = InPort( Bits32 )
       s.out = OutPort( Bits32 )
+      s.set_metadata( VerilogPlaceholderPass.src_file, dirname(__file__)+'/VRegTrace.v' )
       s.set_metadata( VerilogPlaceholderPass.port_map, {
           s.in_ : "d", s.out : "q",
       } )
@@ -494,6 +506,7 @@ def construct( s ):
       s.in_ = InPort( 10 )
       s.out = OutPort( 10 )
       s.vcd_en = OutPort()
+      s.set_metadata( VerilogPlaceholderPass.src_file, dirname(__file__)+'/VIncr.v' )
       s.set_metadata( VerilogPlaceholderPass.has_clk, False )
       s.set_metadata( VerilogPlaceholderPass.has_reset, False )
       s.set_metadata( VerilogVerilatorImportPass.vl_trace, True )

diff --git a/pymtl3/passes/backends/verilog/tbgen/test/VerilogTBGenPass_test.py b/pymtl3/passes/backends/verilog/tbgen/test/VerilogTBGenPass_test.py
@@ -6,6 +6,7 @@
 """Test if the imported object works correctly."""
 
 import pytest
+from os.path import dirname
 
 from pymtl3 import DefaultPassGroup
 from pymtl3.datatypes import Bits1, Bits32, Bits48, Bits64, clog2, mk_bits
@@ -47,6 +48,7 @@ def construct( s, data_width, num_entries, count_width ):
       s.enq_en  =  InPort( Bits1  )
       s.enq_rdy = OutPort( Bits1  )
       s.enq_msg =  InPort( mk_bits( data_width ) )
+      s.set_metadata( VerilogPlaceholderPass.src_file, dirname(__file__)+'/VQueue.v' )
       s.set_metadata( VerilogTranslationImportPass.enable, True )
   num_entries = 1
   q = VQueue(