v7.0.0

Added

• Fast virtual boot mode to accelerate simulation of software on RTL platform
• Added support for Bender as dependency management tool
• Support for ZSH for the VSIM setup script (setup/vsim.sh)
• Added new HyperFlash peripheral
• Added additional bootmode signal to accomodate for new Hyperflash boot

Changed

• HWPE MAC unit is disabled by default
• The latest version of IPApprox with semver support is now used
• Bump pulp_soc to v3.0.0 and updated bootcode to add support for the newest
  PULPissimo compatible version of ibex with a new OBI to TCDM protocol adapter.
• Various smaller clean-ups and improvements of the Makefiles and simulation TCL scripts
• The FPGA ports no longer generate the memories out-of-context.
  Thus, chaning the memory size in RTL now also affects the FPGA memory size.
• Switched to new I2C peripheral version with command stream interface

Fixed

• Resolved incompatibility with Vivao 2020.2
• Resolved incompatibility with Genus 2019.10
  (Genus support still requires to remove some SV attributes from the source code due to some issues in Genus' parser)
  Executing find . -type f -name '*.sv' -exec sed -i -e 's/(\* async \*)//g' {} \;
  in the project root after checking out the sub-ips should do the trick.
• Added better handshaking behavior of mockup FLL modules in FPGA port to avoid
  deadlocks when trying to interact with the FLL in the FPGA port.
• With pulp_soc v3.0.0 a serious bug in the interleaved SRAM address line
  connection is fixed which caused part of the memory to be inaccessible.
• Remove timing constraints on unmapped signals for FPGA ports
• Reduced latency of APB and AXI transactions

Removed

• Removed support for Xilinx Zedboard. With the latest feature additions, the
  Zedboard is no longer large enough to fit the pulpissimo design. The necessary
  scripts to synthesize pulpissimo for the Zedboard will remain in the fpga
  directory but the bitstream generation flow will fail due to insuffienct LUTs available.

v6.0.0

Changed

• Bump pulp_soc to v2.0.0 which adds completely new interconnect with integrated AXI crossbar for simplified IP
  integration
• Make number of SPI and I2C peripherals parametrizable
• Various FPGA tcl script enhancements
• Various rtl code cleanups and assertion additions

Added

• Fixed synthesis issues. PULPissimo is now synthesizable as is.
• Revamped datasheet & added datasheet generator
• CI support for pulp-runtime to run tests, using bwruntest.py and
  tests/runtime-tests.yaml
• CI target for all supported fpga boards
• Point to simple runtime in README.md
• Allow passing generate-scripts to pass arguments to vlog
  ⁻ Add global address space header file for new SoC interconnect in pulp_soc v2.0.0
• Embedded bootcode into repository and added new make target for it
• FPGA support for Nexys board familly
• Add pulp-sdk build target

Fixed

• Properly propagate NB_CORES
• Mark tb as not synthesizable
• Add proper timing constraints for CDCs in FPGA port
• Added missing implementation of manual clock gating cells for FPGA ports

v5.0.0

Added

• FPGA support for Xilinx ZCU102
• FPGA support for Nexys Video
• FPGA support for Zedboard
• ibex support
• Improved software debugging (disassembly in simulator window)
• Gitlab CI (fpga synthesis, software tests, debug module tests)
• Automatic handling of VIPs (installing and compiling)
• CHANGELOD.md

Changed

• Bump pulp_soc to v1.0.0
• Move tests to subfolder tests
• Allow setting entry point with -gENTRY_POINT
• Update to sdk-release 2019.11.02

Fixed

• I2C EEPROM can now be concurrently used with I2C DPI model
• Small quartus compatibility fixes
• Many minor tb issues

Removed

• zero-riscy support

v4.0

• Add support for genesys2 and ZCU104 FPGA boards
• Add suppport for Xcelium/ncsim
• Fix bugs in debug module integration

v1.0

This year ETH Zurich and University of Bologna are celebrating 5 years of collaboration on the PULP project, and we will be sharing a number of designs that we have been working on these past years. Today we are happy to announce PULPissimo, a new single-core RISC-V based open-source microcontroller system which is a significant step ahead in terms of efficiency and completeness with respect to the more basic PULPino, offering a number of new features, such as:

Autonomous Input/Output subsystem (uDMA) that allows data to be directly copied from peripherals to memory, with much improved energy efficiency.
New memory subsystem for improved performance and power management
Support for hardware accelerators that access memories directly. We provide examples of on how to include your own so called Hardware Processing Engines (HWPEs) into PULPissimo
A brand new interrupt controller
Additional peripherals such as the flexible Camera Parallel Interface (CPI) interface for low power image sensors like products of OMNIVISION or the I2S peripheral to support microphones like the ST MP34DT01-M
New SDK with a custom operating-system optimized for uDMA and makefile-based application build process.
PULPissimo, like its smaller brother PULPino, is a single-core platform and supports all our 32-bit RISC-V cores: RI5CY, as well as Zero- and Micro-RI5CY. You can access PULPissimo directly from our GitHub page. We will be continuously updating PULPissimo with code and application examples. And do not forget to follow us on Twitter (@pulp_platform).